Fair And Demand Request Modes; Vme Bus Release; Addressing Capabilities - Caen V2718 Technical Information Manual

Document type: Title:
User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge

2.1.1. Fair and Demand Request modes

The V2718 produces requests on all VME bus request levels: BR3*, BR2*, BR1*, and
BR0*. The default setting is for level 3 VME bus request. The request level is a global
programming option set through the Bus Request field in the Control register (see
§ 2.13.2).
The programmed request level is used by the VME bus Master Interface regardless of
the channel currently accessing the VME bus Master Interface.
The Requester may be programmed for either Fair or Demand mode. The request mode
is a global programming option set through the Requester Type bit in the Control register.
In Fair mode, the V2718 does not request the VME bus until there are no other VME bus
requests pending at its programmed level. This mode ensures that every requester on an
equal level has access to the bus.
In Demand mode, the requester asserts its bus request regardless of the state of the
BRn* line. By requesting the bus frequently, requesters far down the daisy chain may be
prevented from ever obtaining bus ownership. This is referred to as "starving" those
requesters. Note that in order to achieve fairness, all bus requesters in a VME bus
system must be set to Fair mode.

2.1.2. VME bus Release

The Requester can be configured as either RWD (release when done) or ROR (release
on request) using the Release Type bit in the Control register. The default setting is for
RWD: the bus is released as soon as the VME access is terminated; in case of
BLT/MBLT cycles, the access is terminated either when the N required bytes are
transferred (although the cycle is divided into several blocks according to the VME
boundaries) or when BERR* is asserted. ROR means the master releases BBSY* only if
a bus request is pending from another VMEbus master and once the channel that is the
current owner of the VME bus Master Interface is done. Ownership of the bus may be
assumed by another channel without re-arbitration on the bus if there are no pending
requests on any level on the VME bus.

2.2. Addressing capabilities

V2718 generates A16, A24, A32, CR/CSR and LCK address phases on the VME bus.
Address Modifiers of any kind (supervisor/non-privileged and program/data) are also
programmed through the PCI bus: the V2718 does not handle the AM: the PC Host
passes them via PCI as VME cycle parameters. The AM broadcasting depends on the
PC drivers.
The master generates ADdress-Only-with-Handshake (ADOH) cycles in support of lock
commands for A16, A24, and A32 spaces.
Supported addressing:
A16, A24, A32, CR/CSR
A16, A24, A32
A16, A24, A32
ADO
ADOH
NPO:
00106/03:V2718.MUTx/11
for R/W, RMW, ADO and ADOH
for BLT
for MBLT
Address Only
Address Only with Handshake
Filename:
V2718_REV11.DOC
Revision date: Revision:
03/07/2018 11
Number of pages:
79
Page:
13