Block Diagram; Fig. 1: Mod. V2718 Block Diagram - Caen V2718 Technical Information Manual

Document type: Title:
User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge

1.2. Block diagram

CONET
x88
x5
x2
The FPGA (Field Programmable Gate Array) is the module's core; it implements the
CONET communication protocol, the LED display and I/O connectors management on
the front side and the VME Master on the backside.
A 128 kbyte buffer allows to provide a temporary data storage during VME cycles: the
VME data rate is thus decoupled from the PCI rate and may take place at full speed.
NPO:
00106/03:V2718.MUTx/11
V2718
4Mbit FLASH
(FPGA FIRMWARE +
STD
USER DEFINED)
uC
FW
BCK
BOOT
LOAD
A2719
LOCAL BUS
CONET
INTERFACE
INTERF.
DATA-WAY
DISPLAY
NIM/TTL
CONTROL
I/Os
A2818
FPGA
LOCAL BUS
INTERFACE
BOOT
LOAD
STD
uC
FW
BCK
4Mbit FLASH
(FPGA FIRMWARE +
USER DEFINED)

Fig. 1: Mod. V2718 block diagram

Filename:
V2718_REV11.DOC
Revision date:
03/07/2018
128K SRAM
BUFFER
FPGA
MASTER
SYSTEM
CONTROLLER
RAM
SLAVE
16x32
VME CYCLE
MONITOR
I/O
PLX-9054
PCI
INTERFACE
256K SRAM
BUFFER
Revision:
11
Number of pages: Page:
79 10