Motorola MTR2000 T5544 Instruction / Field Service Manual page 184

Station Control Modules
SPI I/O Circuitry
Station Reference Circuitry
6
The Serial Peripheral Interface (SPI) I/O circuitry provides a SPI bus which is
used as a general-purpose communications bus to allow the Host μP to communi-
cate with other modules in the station. The SPI I/O circuitry also includes an A/
D converter which allows the Host μP to determine (via the SPI bus) the connect-
ed optional modules and other station characteristics.
The SCM is always configured as the SPI bus master, while other modules (Re-
ceiver, Exciter, PA, etc.) are configured as bus slaves. Two slave configurations
are possible:
• Basic slave – these are SPI-compatible ICs, located on the slave modules
(e.g., A/D and D/A converters, and frequency synthesizers).
• Intelligent slave – these are slave modules which contain a microprocessor
having a local SPI bus (e.g., intelligent equipment connected to the station
via the Systems connector on the backplane).
There are three SPI signals, as follows:
SPI CLK – derived from the internal Host μP clock. With a Host μP clock
•
frequency of 20.4 MHz, the minimum SPI CLK is approximately 319 KHz.
It is used to shift serial data from the Host μP to a slave, and from the slave
back to the Host μP.
• MOSI (Master Out Slave In) – provides the data path containing information
from the master (SCM) to the slave (Receiver, Exciter, PA, etc.). This is an
output from the Host μP.
• MISO (Master In Slave Out) – provides the data path containing information
from the slave to the master. This is an input to the Host μP.
The Station Reference Circuitry incorporates a high-stability VCO (CMAC Oscil-
lator Circuitry) to generate a stable 16.8 MHz signal which is fed to the DSP
ASIC. The ASIC divides the signal by 8 and outputs a 2.1 MHz signal which is
buffered and filtered by a splitter and output to the Exciter Module and Receiver
Module as 2.1 MHz REF.
The CLN1465 SCM includes a phase-locked loop (PLL) IC. Higher stability is
achieved by phase-locking the CMAC Oscillator Circuitry to a 5/10 MHz external
reference source from an external high-stability oscillator, allowing the CMAC
Oscillator Circuitry to be automatically adjusted to this source (referred to as "au-
to-netting").
68P81096E32-E
08/06/07