Control Bits (E5H); J5 Smbus Enable (E6H) - Intel NetStructure ZT 5504 Manual

Geographic Addressing (E4h), continued
4:0 Geographic Addressing
CompactPCI defines several signal additions to the PCI specification. One of these
is GA[4..0], used for geographic addressing on the backplane. Geographic
addressing uniquely differentiates each board based upon the physical slot into
which it was inserted. Each backplane connector in a CompactPCI system has a
unique code for GA[4..0]. See the
2.1 for more information on geographic addressing. The bits correspond to signals
as follows:
Bit 0 = GA0; Bit 1 = GA1; Bit 2 = GA2; Bit 3 = GA3; Bit 4 = GA4.
A logical 0 indicates that the corresponding GA pin is open. A logical 1 indicates that
the corresponding GA pin is low (GND).

Control Bits (E5h)

Address Offset: E5h
Default Value: 0x00
Size: 8 bits
Attribute: W
Bit Description
7:0 RESERVED

J5 SMBus Enable (E6h)

Address Offset: E6h
Default Value: 0x00
Size: 8 bits
Attribute: W
Bit Description
7 J5 SMBus Enable
This bit enables SMBus function through the rear panel J5 connector. A logical 1
enables this function.
6:0 RESERVED
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CompactPCI Specification, PICMG 2.0, Version
C. System Registers
77