Intel NetStructure ZT 5504 Manual page 14

System master processor board
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• Built-in numeric coprocessor support
• 16 KB of CPU instruction cache
• 16 KB of CPU data cache
• 256 KB of Level 2 cache
• 512 MB or 1 GB of ECC SDRAM
• BIOS stored in flash memory
• Standard AT* Systems include:
– Two enhanced interrupt controllers (8259)
– Three counter/timers (one 8254)
– Real-time clock/CMOS RAM (146818)
– Two enhanced DMA controllers (8237)
– 8042 compatible keyboard controller
– Speaker interface
– PS/2 mouse and keyboard
• Dual stage watchdog timer
• Intel® 69000 series AGP graphics chip
• IPMI through an Intel® Baseboard Management Controller chip
• Dual 10/100 Mbit/s Ethernet* (available at the faceplate or the J3 backplane connector)
• Primary IDE channel supports the on-board 2.5 inch hard disk and an IDE device (CD-ROM)
on a media expansion board
• Single on-board PCI Mezzanine Card (PMC) slot, 32-bit @ 33 MHz using 3.3V signaling
• Two 16C550 RS-232 serial ports (COM1 available at the faceplate, COM1 and COM2
available through the J5 backplane connector)
• Push Button Reset on the front panel
• Rear-Panel I/O Availability (at J5) includes the following
– Secondary IDE channel
– Rear panel eject
– Push-button reset input
• DC power monitors (+3.3V, +5V, +12V, -12V, and CPU core voltage)
• Support for Windows* 2000 Professional, Windows 2000 Server, Linux*, and VxWorks*
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1. Introduction
13

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