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1 Perform the normal and complement tests for each additional pod on the
NOTE:
1 Disconnect the E5383A Flying Lead Probe from Pod 6 of the 16910A logic
2 From the Logic Analysis System main menu, select Setup→My
3 In the State Options section, Sampling Options field, select the "500 MHz"
4 In the logic analyzer's Buses/Signals window, unassign all bits.
Chapter 3: Testing Logic Analyzer Performance
Test the Remaining Pods in 250 Mb/s Mode
Test the Remaining Pods in 250 Mb/s Mode
logic analyzer, changing the connection to the pod, channel assignments,
thresholds, etc. as appropriate. Test using clock Clk3 for Pod 3, clock Clk4
for Pod 4, etc. Upon completion, the logic analyzer is completely tested in
the 250 Mb/s mode. The 16910A has six pods; the 16911A has four pods.
Test Pod 1 in 500 Mb/s Mode
If option 500 is not installed on the 16910/11A module, then 250 MHz will
be the only speed available. In this case, write "n/a" in the 500Mb/s mode
boxes in the Performance Test Record and proceed to "Conclude the State
Mode Tests" on page 59.
Clock "Clk1" will be used for testing all pods in the 500 Mb/s mode.
Therefore two E5383A Flying Lead Probe sets will be required when
testing the remaining pods.
You will use a test frequency of 125 MHz (plus test margin) to determine
the correct eye in the Eye Finder window. Then you will increase the test
frequency to 250 MHz (plus test margin) and perform the test.
analyzer (or from Pod 4 of the 16911A logic analyzer) and connect it to
Pod 1 of the logic analyzer.
1691xA→Timing/State (Sampling)...
mode. The clock mode will change to "Both Edges". No other mode is
available.
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