Altera Nios II Cyclone Edition Reference Manual page 53

A
Appendix A
Shared bus table
Appendix C
Connecting to the Board via Ethernet
B
Block diagram 1–2
Board Ethernet connection
Browse the board
Connecting the Ethernet cable
Connecting the LCD display
Obtaining an IP Address
C
Clock circuitry 1–28
CompactFlash connector
Configuration and reset buttons
SW10 - Reset config
SW8 - CPU reset
SW9 - Safe config
Configuration controller device
Configuration data
Configuration-status LEDs
Cyclone configuration
Reset distribution
Safe and user configurations
Starting configuration
Configuration-status LEDs
Indicators 1–26
Conventional flash memory usage
Cyclone EP1C20 device
D
Development board
Features 1–1
Altera Corporation
December 2004
A–1
C–1
C–5
C–1
C–2
C–2
1–6
1–26
1–27
1–26
1–27
1–20
1–22
1–25
1–21
1–21
1–22
1–21
1–23
1–4
General description
Dual 7-segment display
U8 & U9 pin information
Dual SRAM devices
E
Ethernet PHY/MAC
Expansion connector header (PROTO1)
J11 pin information
J12 pin information
J13 pin information
Expansion connector header (PROTO2)
J15 pin information
J16 pin information
J17 pin out information
F
Flash memory allocation
Flash memory device
I
Individual LEDs (D0 - D7)
Pin information
J
JTAG connections
JTAG to Cyclone device (J24)
JTAG to MAX device (J5)
JTAG connectors 1–29
M
Mictor connector 1–15
Debug port to OCI debug module
J25 pin information
Index
1–1
1–18
1–18
1–10
1–11
1–11
1–12
1–13
1–13
1–13
1–15
1–14
1–15
1–23
1–5
1–19
1–19
1–29
1–30
1–16
1–17
Index–1