Altera Nios II Cyclone Edition Reference Manual page 43

Table A–9. Shared Bus Table (Part 3 of 3)
NET Name
Description
FLASH_CS_n Chip Select
FLASH_OE-N Read Enable
FLASH_RW-N Write Enable
FLASH_RY-BY_N Ready/Busy
SRAM_BE_N0 Byte Enable 0 IO
SRAM_BE_N1 Byte Enable 1 IO
SRAM_BE_N2 Byte Enable 2 IO
SRAM_BE_N3 Byte Enable 3 IO
SRAM_CS_N Chip Select
SRAM_OE_N Read Enable
SRAM_WE_N Write Enable
ENET_ADS_N Address
Strobe
ENET_AEN Address
Enable
ENET_BE_N0 Byte Enable 0 IO
ENET_BE_N1 Byte Enable 1 IO
ENET_BE_N2 Byte Enable 2 IO
ENET_BE_N3 Byte Enable 3 IO
ENET_CYCLE_N Bus Cycle
ENET_DATACS_N Data Chip
Select
ENET_INTRQ0 Interrupt
ENET_IOCHRDY IO Char
Ready
ENET_IOR_N Read
ENET_IOW_N Write
ENET_LCLK Local Bus
Clock
ENET_LDEV_N Local Device
ENET_RDYRTN_N Ready Return IO
ENET_W_R_N Write/Read
Altera Corporation
December 2004
PLD (U60)
NET
Pin
Pin #
Name
IO A12
IO B12
IO D12
IO C12
V17
V16
W16
T16
IO W17
IO Y17
IO U16
IO A14
IO B15
C16
B16
D16
E16
IO B17
IO C15
IO D15
IO F14
IO A15
IO E15
IO C17
IO D3
B18
IO A17
Flash (U5) SRAM (U35) SRAM (U36) Ethernet (U4)
Pin Pin
Pin #
Name Name
CE_n 28
OE_n 30
WE_n 11
RY/BY_ 14
n
BE0#
BE1#
CS_n
OE_n
WE_n
Pin Pin
Pin # Pin #
Name Name
39
40
BE2# 39
BE3# 40
6 CS_n 6
41 OE_n 41
17 WE_n 17
ADS#
AEN
BE0#
BE1#
BE2#
BE3#
CYCLE
#
DATAC
S#
INTRO
ARDY
RD#
WR#
LCLK
LDEV#
RDYRT
N#
W/R#
Pin #
37
41
94
95
96
97
35
34
29
38
31
32
42
45
46
36
A–3