Appendix A. Shared Bus Table - Altera Nios II Cyclone Edition Reference Manual

Description
Table A–9. Shared Bus Table (Part 1 of 3)
NET Name
Description
FSE_A0 Shared
Address
FSE_A1
FSE_A2
FSE_A3
FSE_A4
FSE_A5
FSE_A6
FSE_A7
FSE_A8
FSE_A9
FSE_A10
FSE_A11
FSE_A12
FSE_A13
FSE_A14
FSE_A15
FSE_A16
FSE_A17
FSE_A18
FSE_A19
FSE_A20
FSE_A21
FSE_A22
Altera Corporation
December 2004
On the Nios development board, Cyclone Edition, the flash memory,
SRAM, and Ethernet MAC/PHY devices share address and control lines.
These shared lines are referred to as the Shared Bus. Using SOPC Builder,
designers can interface a Nios II processor system to any device
connected to the off-chip Shared Bus.
connections between the devices connected to the Shared Bus.
PLD (U60)
NET
Pin
Pin #
Name
IO B4
IO A4
IO D5
IO D6
IO C5
IO B5
IO C2
IO D2
IO D4
IO D1
IO E4
IO E5
IO F3
IO E3
IO E2
IO F4
IO F5
IO F2
IO F1
IO F6
IO G5
IO G1
IO G2

Appendix A. Shared Bus Table

Flash (U5) SRAM (U35) SRAM (U36) Ethernet (U4)
Pin Pin
Pin #
Name Name
A0 27
A1 22
A2 21 A0
A3 20 A1
A4 19 A2
A5 18 A3
A6 17 A4
A7 16 A5
A8 10 A6
A9 9 A7
A10 42 A8
A11 8 A9
A12 7 A10
A13 6 A11
A14 5 A12
A15 4 A13
A16 3 A14
A17 46 A15
A18 15 A16
A19 43 A17
A20 44
A21 35
A22 2
Table A–9 on page A–1
Pin
Pin # Pin #
Name Name
A1
1 A0 1 A2
2 A1 2 A3
3 A2 3 A4
4 A3 4 A5
5 A4 5 A6
18 A5 18 A7
19 A6 19 A8
20 A7 20 A9
21 A8 21 A10
22 A9 22 A11
23 A10 23 A12
24 A11 24 A13
25 A12 25 A14
26 A13 26 A15
27 A14 27
42 A15 42
43 A16 43
44 A17 44
lists all
Pin
Pin #
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
A–1