Altera Nios II Cyclone Edition Reference Manual page 17

Altera Corporation
December 2004
The SDRAM device pins are connected to the Cyclone device (see
Table 1–3 on page 1–9). An SDRAM controller peripheral is included with
the Nios II development kit, allowing a Nios II processor to view the
SDRAM device as a large, linearly-addressable memory.
Table 1–3. SDRAM (U57) Pin Table (Part 1 of 2)
Pin Name
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA0
BA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Nios Development Board Reference Manual, Cyclone Edition
Pin Number Connects to Cyclone Pin
25 M2
26 M1
27 M6
60 M4
61 J8
62 J7
63 J6
64 J5
65 J4
66 J3
24 H6
21 H5
22 H7
23 H1
2 M5
4 M3
5 M7
7 N6
8 N1
10 N2
11 N4
13 N3
74 N5
76 N7
77 P7
79 P2
80 P1
82 P6
83 P5
85 P3
Board Components
1–9