Mdio Control Register (Control); Mdio Control Register (Control) Field Descriptions - Texas Instruments TMS320C674X User Manual

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4.2

MDIO Control Register (CONTROL)

The MDIO control register (CONTROL) is shown in
31 30 29
IDLE ENABLE Rsvd
R-1 R/W-0 R-0
15
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing a 0 has no effect); -n = value after reset
Bit Field
31 IDLE
30 ENABLE
29 Reserved
28-24 HIGHEST_USER_CHANNEL
23-21 Reserved
20 PREAMBLE
19 FAULT
18 FAULTENB
17-16 Reserved
15-0 CLKDIV
SPRUFL5B – April 2011
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Figure 26. MDIO Control Register (CONTROL)
28 24
HIGHEST_USER_CHANNEL
R-1
Table 24. MDIO Control Register (CONTROL) Field Descriptions
Value Description
State machine IDLE status bit.
0 State machine is not in idle state.
1 State machine is in idle state.
State machine enable control bit. If the MDIO state machine is active at the time it is
disabled, it will complete the current operation before halting and setting the idle bit.
0 Disables the MDIO state machine.
1 Enable the MDIO state machine.
0 Reserved
0-1Fh Highest user channel that is available in the module. It is currently set to 1. This
implies that MDIOUserAccess1 is the highest available user access channel.
0 Reserved
Preamble disable
0 Standard MDIO preamble is used.
1 Disables this device from sending MDIO frame preambles.
Fault indicator. This bit is set to 1 if the MDIO pins fail to read back what the device
is driving onto them. This indicates a physical layer fault and the module state
machine is reset. Writing a 1 to this bit clears this bit, writing a 0 has no effect.
0 No failure
1 Physical layer fault; the MDIO state machine is reset.
Fault detect enable. This bit has to be set to 1 to enable the physical layer fault
detection.
0 Disables the physical layer fault detection.
1 Enables the physical layer fault detection.
0 Reserved
0-FFFFh Clock Divider bits. This field specifies the division ratio between the peripheral clock
and the frequency of MDIO_CLK. MDIO_CLK is disabled when CLKDIV is cleared to
0. MDIO_CLK frequency = peripheral clock frequency/(CLKDIV + 1).
© 2011, Texas Instruments Incorporated
Figure 26 and described in
23 21 20
Reserved PREAMBLE
R-0 R/W-0
CLKDIV
R/W-FFh
MDIO Registers
Table 24.
19 18 17
FAULT FAULTENB Reserved
R/W1C-0 R/W-0 R-0
EMAC/MDIO Module
16
0
71