Texas Instruments TMS320C674X User Manual page 7

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47 Transmit Interrupt Mask Set Register (TXINTMASKSET)
48 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)
49 MAC Input Vector Register (MACINVECTOR)
50 MAC End Of Interrupt Vector Register (MACEOIVECTOR)
51 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)
52 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)
53 Receive Interrupt Mask Set Register (RXINTMASKSET)
54 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
55 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)
56 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)
57 MAC Interrupt Mask Set Register (MACINTMASKSET)
58 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
59 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)
60 Receive Unicast Enable Set Register (RXUNICASTSET)
61 Receive Unicast Clear Register (RXUNICASTCLEAR)
62 Receive Maximum Length Register (RXMAXLEN)
63 Receive Buffer Offset Register (RXBUFFEROFFSET)
64 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
65 Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH)
66 Receive Channel n Free Buffer Count Register (RXnFREEBUFFER)
67 MAC Control Register (MACCONTROL)
68 MAC Status Register (MACSTATUS)
69 Emulation Control Register (EMCONTROL)
70 FIFO Control Register (FIFOCONTROL)
71 MAC Configuration Register (MACCONFIG)
72 Soft Reset Register (SOFTRESET)
73 MAC Source Address Low Bytes Register (MACSRCADDRLO)
74 MAC Source Address High Bytes Register (MACSRCADDRHI)
75 MAC Hash Address Register 1 (MACHASH1)
76 MAC Hash Address Register 2 (MACHASH2)
77 Back Off Random Number Generator Test Register (BOFFTEST)
78 Transmit Pacing Algorithm Test Register (TPACETEST)
79 Receive Pause Timer Register (RXPAUSE)
80 Transmit Pause Timer Register (TXPAUSE)
81 MAC Address Low Bytes Register (MACADDRLO)
82 MAC Address High Bytes Register (MACADDRHI)
83 MAC Index Register (MACINDEX)
84 Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP)
85 Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP)
86 Transmit Channel n Completion Pointer Register (TXnCP)
87 Receive Channel n Completion Pointer Register (RXnCP)
88 Statistics Register
SPRUFL5B - April 2011
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© 2011, Texas Instruments Incorporated
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List of Figures
7