Receive Maximum Length Register (Rxmaxlen); Receive Buffer Offset Register (Rxbufferoffset); Receive Maximum Length Register (Rxmaxlen) Field Descriptions; Receive Buffer Offset Register (Rxbufferoffset) Field Descriptions - Texas Instruments TMS320C674X User Manual

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5.24 Receive Maximum Length Register (RXMAXLEN)

The receive maximum length register (RXMAXLEN) is shown in
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 61. Receive Maximum Length Register (RXMAXLEN) Field Descriptions
Bit Field
31-16 Reserved
15-0 RXMAXLEN

5.25 Receive Buffer Offset Register (RXBUFFEROFFSET)

The receive buffer offset register (RXBUFFEROFFSET) is shown in
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 62. Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions
Bit Field
31-16 Reserved
15-0 RXBUFFEROFFSET
SPRUFL5B – April 2011
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Figure 62. Receive Maximum Length Register (RXMAXLEN)
Value Description
0 Reserved
0-FFFFh Receive maximum frame length. These bits determine the maximum length of a received frame.
The reset value is 5EEh (1518). Frames with byte counts greater than RXMAXLEN are long
frames. Long frames with no errors are oversized frames. Long frames with CRC, code, or
alignment error are jabber frames.
Figure 63. Receive Buffer Offset Register (RXBUFFEROFFSET)
RXBUFFEROFFSET
Value Description
0 Reserved
0-FFFFh Receive buffer offset value. These bits are written by the EMAC into each frame SOP
buffer descriptor Buffer Offset field. The frame data begins after the RXBUFFEROFFSET
value of bytes. A value of 0 indicates that there are no unused bytes at the beginning of
the data, and that valid data begins on the first byte of the buffer. A value of Fh (15)
indicates that the first 15 bytes of the buffer are to be ignored by the EMAC and that valid
buffer data starts on byte 16 of the buffer. This value is used for all channels.
© 2011, Texas Instruments Incorporated
Figure 62
Reserved
R-0
RXMAXLEN
R/W-5EEh
Figure 63
Reserved
R-0
R/W-0
EMAC Module Registers
and described in Table 61.
and described in Table
EMAC/MDIO Module
16
0
62.
16
0
107