Subscribe to Our Youtube Channel
Related Manuals for Texas Instruments TMS320DM646 Series
Summary of Contents for Texas Instruments TMS320DM646 Series
- Page 1 TMS320DM646x DMSoC ATA Controller User's Guide Literature Number: SPRUEQ3 December 2007...
- Page 2 SPRUEQ3 – December 2007 Submit Documentation Feedback...
-
Page 3: Table Of Contents
Contents ..........................Preface ........................ Introduction ..................Purpose of the Peripheral ......................Features ..................Functional Block Diagram ................... Supported Use Cases ................Industry Standard(s) Compliance ................Terminology Used in This Document ....................... Architecture ..................... Clock Control ..................... Signal Descriptions ....................Pin Multiplexing .................. - Page 4 List of Figures ..................... ATA Controller Block Diagram ................ Physical Region Descriptor (PRD) Table Entry ..............Primary IDE Channel DMA Control Register (BMICP) ..............Primary IDE Channel DMA Status Register (BMISP) .......... Primary IDE Channel DMA Descriptor Table Pointer Register (BMIDTP) ..............
-
Page 5: Preface
SPRAA84 — TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The objective of this document is to indicate differences between the two cores. Functionality in the devices that is identical is not included. - Page 6 Related Documentation From Texas Instruments SPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache.
-
Page 7: Introduction
User's Guide SPRUEQ3 – December 2007 ATA Controller Introduction The AT attachment/ATA packet interface (ATA/ATAPI), also known as IDE controller, is the traditional choice of the communication medium between a portable computer (PC) and a hard-disk drive. Ever since its adoption by the industry, it has been the choice of interface between a PC and a common storage medium. -
Page 8: Functional Block Diagram
www.ti.com Introduction Functional Block Diagram The ATA controller is shown in Figure Figure 1. ATA Controller Block Diagram Peripheral IDE Timing ARM CPU Interface Control IDE Controller Register File ATA_INTRQ ATA_IORDY ATA_DMARQ ATA_DMACK Interrupt Interrupt Controller ATA CS0 ATA CS1 IDE Host ATA_HA0 System... -
Page 9: Industry Standard(S) Compliance
www.ti.com Architecture Industry Standard(s) Compliance The IDE controller supports the ATA/ATAPI-6 and compact Flash v2.0 specifications. The specific modes of operations (PIO, multiword, and ultra-DMA) depend on the frequency at which the IDE controller operates. For this reason, not all modes supported by the specification and device may be exercised if the clocking frequency to the IDE controller is low. -
Page 10: Signal Descriptions
www.ti.com Architecture Signal Descriptions 2.2.1 ATA/ATAPI Interface Signals Supported by the ATA Controller Table 1 describes the signals supported by the IDE controller interface. Table 1. Supported ATA Controller Signals Direction from Terminal Name IDE Controller Description ATA_CS0 Output Chip Select Signals 0 and 1 ATA_CS1 These are the chip select signals from the host used to select the Command Block or Control Block registers. - Page 11 www.ti.com Architecture Table 1. Supported ATA Controller Signals (continued) Direction from Terminal Name IDE Controller Description ATA_HIOR Output PIO Read Transaction Indicator DMA Ready during Ultra-DMA Read DMA Data Strobe during Ultra-DMA Write ATA_HIOR is the strobe signal used by the host to read device registers or data. Data is transferred on the negation of this signal.
-
Page 12: Pin Multiplexing
www.ti.com Architecture 2.2.2 ATA/ATAPI/Compact Flash Specification Signals Not Supported by This Peripheral The processor supports all the signals needed to realize the supported modes of operation. Table 2 lists some of the signals that are present within the ATA/ATAPI specification that are not available. In addition, the processor supports additional signals to interface to devices that are 3.3 V and 5.0 V tolerant devices. -
Page 13: General Architecture
www.ti.com Architecture General Architecture 2.5.1 Programmable Timing Registers The IDE controller implements several programmable timing registers that allow users to reprogram the key IDE interface signal timings for the four transfer types: 8-bit task file registers accesses, 16-bit PIO data accesses, multiword DMA transfers, and ultra-DMA transfers. This allows the host controller to effectively be reconfigured to support a wide range of input clock frequencies and any target interface for all transfer types. - Page 14 www.ti.com Architecture 2.5.1.1 Programming 8-bit Task File Timing Registers The REGSTB, REGRCVR, and MISCCTL are used in reprogramming the timings for 8-bit task file register accesses. The required IDE timing parameters for 8-bit task file register accesses are defined in the ATA/ATAPI-6 specification.
- Page 15 www.ti.com Architecture 2.5.1.2 Programming Data Register Timing Register Access The DATSTB and DATRCVR are used in reprogramming the timings for 16-bit PIO data accesses. The required IDE timing parameters for 8-bit task file register accesses are defined in the ATA/ATAPI-6 specification.
- Page 16 www.ti.com Architecture 2.5.1.3 Programming Multiword DMA Register Accesses The DMASTB and DMARCVR are used in reprogramming the timings for multiword DMA transfers. The required IDE timing parameters for multiword DMA transfers are defined in the ATA/ATAPI-6 specification. The DMASTB and DMARCVR can be programmed to match the parameters t (cycle time), t (strobe time), and t...
- Page 17 www.ti.com Architecture 2.5.1.4 Programming Ultra-DMA Register Accesses The UDMASTB, UDMATRP, and UDMATENV are used in reprogramming the timings for ultra-DMA transfers. The required IDE timings parameters for ultra-DMA transfers are defined in the ATA/ATAPI-6 specification. The UDMASTB, UDMATRP, and UDMATENV can be programmed to match the parameters t (cycle time), t (two cycle time), t...
-
Page 18: Dma And Pio Data Transaction Overview
www.ti.com Architecture DMA and PIO Data Transaction Overview The IDE controller supports a dedicated DMA controller in order to handle DMA transfers between host memory and attached ATA/ATAPI device. This occurs for both multiword and ultra-DMA transfers during DMA writes to and reads from the device. The DMA controller includes logic to manage the physical region descriptors (PRDs) that describe the DMA transfers, and controls a set of 32-bit wide FIFOs (256-byte read FIFO and 256-byte write FIFO resident within the IDE controller) to temporarily store data for DMA transfers. -
Page 19: Physical Region Descriptor (Prd) Table Entry
www.ti.com Architecture The physical memory region to be transferred is described by a physical region descriptor (PRD). Each PRD entry is 8 bytes in length (Figure 2 Table 3). The first 4 bytes specify the byte address of a physical memory region; the next two bytes specify the count of the region in bytes (64K byte limit per region). - Page 20 www.ti.com Architecture 2.6.1.2 DMA Driven Disk Write Transfer Operation To perform an ATA DMA write operation to an attached ATA/ATAPI device, a physical descriptor region is programmed by firmware indicating a system memory address to transfer data from and the number of bytes to transfer.
- Page 21 www.ti.com Architecture 2.6.1.4 Miscellaneous Cases 2.6.1.4.1 Multiword and Ultra-DMA Abort After any type of DMA transfer has been initiated (multiword or ultra-DMA read or write), firmware is allowed to prematurely abort the transfer. A DMA transfer is initiated when a PRD has been set up and the DMASTART bit in the primary IDE channel DMA control register (BMICP) has been set to 1.
-
Page 22: Attached Device Reset Considerations
www.ti.com Architecture 2.6.1.6 PIO Pre-Fetch/Post-Write Feature The IDE host controller has a pre-fetch/post-write feature that would alleviate, when enabled, the wait time incurred to the host CPU by the slower IDE interface by allowing the CPU to perform burst read/write PIO data accesses. -
Page 23: Initialization
www.ti.com Architecture Initialization Proper host initialization needs to take place prior to accessing attached ATA/ATAPI device. From the host side, the programmable timing registers are required to be programmed appropriately for the type of control (PIO 8-bit) and data (PIO, multiword, or ultra-DMA) transaction to be used. It is important that the programming of the registers on the host side matches the device side mode of operation. - Page 24 www.ti.com Architecture 2.8.1.2 Multiword DMA Initialization It is important that the attached device capability is identified prior to invoking any type of DMA activity. In addition, prior to using a DMA transaction, it is the responsibility of the firmware to configure the mode for the type of DMA transaction to be used (in this case it is multiword DMA, not ultra-DMA).
- Page 25 www.ti.com Architecture 2.8.1.3 Ultra-DMA Initialization It is important that the attached device capability is identified prior to invoking any type of DMA activity. In addition, prior to using a DMA transaction, it is the responsibility of the firmware to configure the mode for the type of DMA transaction to be used.
-
Page 26: Interrupt Support
www.ti.com Architecture 2.8.2 Attached Device Initialization After power-on reset, the attached ATA/ATAPI device comes up in a default mode that might not be known by the host firmware. However, as long as it is a functional device, it should be ready to communicate with the firmware. -
Page 27: Identifying The Ata Controller Interrupt Sources
www.ti.com Architecture Table 5. Identifying the ATA Controller Interrupt Sources Interrupt Source INTRSAT Bit IORDYINT Bit PIO transaction DMA transaction IORDY timeout 2.9.1.1 ATA Interrupt Source: ATA_IORDY (IORDY) Timer The ATA_IORDY (IORDY) timer interrupt is generated by the IDE controller logic when the IDE controller ATA_IORDY (IORDY) timer is programmed with a non-zero value and the device fails to deassert the ATA_IORDY signal before the timer runs out when performing PIO transactions. - Page 28 www.ti.com Architecture 2.9.1.4 Acknowledging Attached Device Interrupt When a device is ready or finished with a data transaction or when a device finishes executing certain commands, it generates an interrupt to the host in order to indicate the completion status. The device communicates its status by asserting the ATA_INTRQ signal.
-
Page 29: 2.10 Edma Event Support
www.ti.com Architecture Table 6. DMA Driven Interrupt Conditions Interrupt Source INTRSTAT IDEACT Device DMA (Host) Description DMA transfer is in progress. Too early to generate an interrupt. The IDE device generated an interrupt and the physical region descriptors have been exhausted. This is normal completion where the size of the physical memory regions is equal to the IDE device transfer size. -
Page 30: 2.11 Power Management
www.ti.com Use Cases 2.11 Power Management The ATA/ATAPI controller can be placed in reduced power modes to conserve power during periods of low activity. The power management of the peripheral is controlled by the processor Power and Sleep Controller (PSC). The PSC acts as a master controller for power management of all of the peripherals on the processor. -
Page 31: Interfacing To A Standard Ata/Atapi Device Through A Level-Shifter
www.ti.com Use Cases 3.1.2 Software Configuration for Interfacing to a Standard ATA/ATAPI Device The following is a recommendation of how the firmware performs a host and device initialization. The initialization steps are: 1. Identify IDE controller clock frequency. 2. Initialize programmable timing registers for PIO mode 0 register access based on the clock frequency. 3. -
Page 32: Interfacing To Compact Flash
www.ti.com Use Cases Table 8. ATA/ATAPI Device Interface Connections for a Standard ATA/ATAPI Device Through a Level-Shifter Processor Attached ATA/ATAPI ATA/ATAPI Controller Signal Device Signal Description ATA_CS[1:0] CS[1:0] Chip select 0 and 1, used by host to select command block and control block registers. -
Page 33: Ata/Atapi Device Interface Connections For A Compact Flash Device
www.ti.com Use Cases Table 9. ATA/ATAPI Device Interface Connections for a Compact Flash Device DM646x Attached ATA/ATAPI ATA/ATAPI Controller Signal Device Signal Description ATA_CS[1:0] CS[2:1] Chip select 0 and 1, used by host to select command block and control block registers, respectively, within the compact Flash device in true-IDE mode. -
Page 34: Registers
www.ti.com Registers Registers Table 10 lists the memory-mapped registers for the ATA controller. See the device-specific data manual for the memory address of these registers. Table 11 lists the registers that are in the attached device, but not in the DM646x processor. Table 10. -
Page 35: Primary Ide Channel Dma Control Register (Bmicp)
www.ti.com Registers Primary IDE Channel DMA Control Register (BMICP) The primary IDE channel DMA control register (BMICP) is a 16-bit wide register used to indicate the direction of the DMA. It is also used to initiate DMA transfers to/from the IDE devices. BMICP is shown in Figure 3 and described in Table... -
Page 36: Primary Ide Channel Dma Status Register (Bmisp)
www.ti.com Registers Primary IDE Channel DMA Status Register (BMISP) The primary IDE channel DMA status register (BMISP) is a 16-bit wide register used to indicate interrupt presence, DMA error condition, as well as DMA activity (state). BMISP is shown in Figure 4 and described Table... -
Page 37: Primary Ide Channel Dma Descriptor Table Pointer Register (Bmidtp)
www.ti.com Registers Primary IDE Channel DMA Descriptor Table Pointer Register (BMIDTP) The primary channel DMA descriptor table pointer register (BMIDTP) is a 32-bit wide register used to describe the starting address of the DMA descriptor table. BMIDTP must be programmed appropriately before setting the DMASTART bit in the primary IDE channel DMA control register (BMICP). -
Page 38: Primary Ide Channel Timing Register (Idetimp)
www.ti.com Registers Primary IDE Channel Timing Register (IDETIMP) The primary IDE channel timing register (IDETIMP) is a 16-bit wide register used to control the enable/disable capability for the IDE interface as well as control for PIO data pre-fetch/post-write capability. IDETIMP is shown in Figure 6 and described in Table... -
Page 39: Ide Controller Status Register (Idestat)
www.ti.com Registers IDE Controller Status Register (IDESTAT) The IDE controller status register (IDESTAT) is an 8-bit wide register used to return the logic value of various IDE interface signals. IDESTAT is shown in Figure 7 and described in Table Figure 7. IDE Controller Status Register (IDESTAT) Reserved DMARQ INTRQ... -
Page 40: Ultra-Dma Control Register (Udmactl)
www.ti.com Registers Ultra-DMA Control Register (UDMACTL) The ultra-DMA control register (UDMACTL) is a 16-bit wide register used to enable each individual drive for ultra-DMA transfers. For multiword DMA (not ultra-DMA) operation, UDMACTL should be programmed with a 0. UDMACTL is shown in Figure 8 and described in Table... -
Page 41: Miscellaneous Control Register (Miscctl)
www.ti.com Registers Miscellaneous Control Register (MISCCTL) The miscellaneous control register (MISCCTL) is a 32-bit wide register used to provide miscellaneous configuration for the IDE controller PIO 8-bit, PIO 16-bit, and multiword DMA write hold time. All three transactions share the same field. The value programmed should be large enough to satisfy all three transfers. -
Page 42: Task File Register Strobe Timing Register (Regstb)
www.ti.com Registers Task File Register Strobe Timing Register (REGSTB) The task file register strobe timing register (REGSTB) is a 32-bit wide register used in conjunction with the TIMORIDE bit in the miscellaneous control register (MISCCTL). REGSTB is used to define the PIO 8-bit transaction strobe assertion time width in clock cycles for both the master and slave devices. -
Page 43: Task File Register Recovery Timing Register (Regrcvr)
www.ti.com Registers Task File Register Recovery Timing Register (REGRCVR) The task file register recovery timing register (REGRCVR) is a 32-bit wide register used in conjunction with the TIMORIDE bit in the miscellaneous control register (MISCCTL). REGRCVR is used to define the PIO 8-bit transaction strobe deassertion time width in clock cycles for both the master and slave devices. -
Page 44: Data Register Access Pio Strobe Timing Register (Datstb)
www.ti.com Registers 4.10 Data Register Access PIO Strobe Timing Register (DATSTB) The data register PIO strobe timing register (DATSTB) is a 32-bit wide register used in conjunction with the TIMORIDE bit in the miscellaneous control register (MISCCTL). DATSTB is used to define the PIO 16-bit data transaction strobe assertion time width in clock cycles for both the master and slave devices. -
Page 45: Data Register Access Pio Recovery Timing Register (Datrcvr)
www.ti.com Registers 4.11 Data Register Access PIO Recovery Timing Register (DATRCVR) The data register PIO recovery timing register (DATRCVR) is a 32-bit wide register used in conjunction with the TIMORIDE bit in the miscellaneous control register (MISCCTL). DATRCVR is used to define the PIO 16-bit data transaction strobe deassertion time width in clock cycles for both the master and slave devices. -
Page 46: Multiword Dma Strobe Timing Register (Dmastb)
www.ti.com Registers 4.12 Multiword DMA Strobe Timing Register (DMASTB) The DMA strobe timing register (DMASTB) is a 32-bit wide register used in conjunction with the TIMORIDE bit in the miscellaneous control register (MISCCTL). DMASTB is used to define the multiword DMA data transaction strobe assertion time width in clock cycles for both the master and slave devices. -
Page 47: Multiword Dma Recovery Timing Register (Dmarcvr)
www.ti.com Registers 4.13 Multiword DMA Recovery Timing Register (DMARCVR) The DMA recovery timing register (DMARCVR) is a 32-bit wide register used in conjunction with the TIMORIDE bit in the miscellaneous control register (MISCCTL). DMARCVR is used to define the multiword DMA data transaction strobe deassertion time width in clock cycles for both the master and slave devices. -
Page 48: Ultra-Dma Strobe Timing Register (Udmastb)
www.ti.com Registers 4.14 Ultra-DMA Strobe Timing Register (UDMASTB) The ultra-DMA strobe register (UDMASTB) is a 32-bit wide register used in conjunction with the TIMORIDE bit in the miscellaneous control register (MISCCTL). UDMASTB is used to define the ultra-DMA data transaction half-strobe width (t ) in clock cycles for both the master and slave devices. -
Page 49: Ultra-Dma Ready-To-Pause Timing Register (Udmatrp)
www.ti.com Registers 4.15 Ultra-DMA Ready-to-Pause Timing Register (UDMATRP) The ultra DMA ready-to-pause timing register (UDMATRP) is a 32-bit wide register used in conjunction with the TIMORIDE bit in the miscellaneous control register (MISCCTL). UDMATRP is used to define the minimum time in clock cycles after ATA_IORDY is negated after which the recipient may assert ATA_HIOW or negate ATA_DMARQ for both the master and slave devices. -
Page 50: Ultra-Dma Timing Envelope Register (Udmatenv)
www.ti.com Registers 4.16 Ultra-DMA Timing Envelope Register (UDMATENV) The ultra-DMA timing envelope register (UDMATENV) is a 32-bit wide register used in conjunction with the TIMORIDE bit in the miscellaneous control register (MISCCTL). UDMATENV is used to define the time in clock cycles when: •... -
Page 51: Primary Io Ready Timer Configuration Register (Iordytmp)
www.ti.com Registers 4.17 Primary IO Ready Timer Configuration Register (IORDYTMP) The primary IO ready timer configuration register (IORDYTMP) is a 32-bit wide register used to enable a timeout value, in CPU clock cycles, for a PIO modes 3 and 4 transaction in order to limit the amount of time a device can extend its wait state to complete its transaction. - Page 52 TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products...
Need help?
Do you have a question about the TMS320DM646 Series and is the answer not in the manual?
Questions and answers