Sdram Refresh Control Register (Sdrcr); Sdram Refresh Control Register (Sdrcr) Field Descriptions - Texas Instruments TMS320C642x DSP User Manual

www.ti.com
4.3

SDRAM Refresh Control Register (SDRCR)

The SDRAM refresh control register (SDRCR) is used to configure the DDR2 memory controller to:
Enter and Exit the self-refresh state.
Enable and disable MCLK, stopping when in the self-refresh state.
Meet the refresh requirement of the attached DDR2 device by programming the rate at which the
DDR2 memory controller issues autorefresh commands.
The SDRCR is shown in
31 30 29
SR MCLKSTOPEN
R/W-0 R/W-0
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 27. SDRAM Refresh Control Register (SDRCR) Field Descriptions
Bit Field
31 SR
30 MCLKSTOPEN
29-24 Reserved
23 Reserved
22-16 Reserved
15-0 RR
SPRUEM4A – November 2007
Submit Documentation Feedback
Figure 21 and described in
Figure 21. SDRAM Refresh Control Register (SDRCR)
Reserved
R-0
Value Description
Self refresh.
0 DDR2 memory controller exits the self-refresh mode.
1 DDR2 memory controller enters the self-refresh mode.
MCLK stop enable.
0 Disables MCLK stopping, MCLK may not be stopped.
1 Enables MCLK stopping, MCLK may be stopped. The SR bit must be set to 1 before setting the
MCLKSTOPEN bit to 1.
0 Reserved
0 Reserved. Always write 0 to this bit.
0 Reserved
0-FFFFh Refresh rate. Defines the rate at which the attached DDR2 devices will be refreshed. The value
of this field may be calculated with the following equation:
RR = DDR2 clock frequency (in MHZ)
where DDR2 refresh rate is derived from the DDR2 data sheet. Writing a value < 0100h to this
field causes it to be loaded with the value 2
(SDTIMR).
Table 27.
24 23 22
Rsvd
R/W-0
RR
R/W-884h
DDR2 refresh rate (in s)
T_RFC from the SDRAM timing register
DDR2 Memory Controller Registers
Reserved
R-0
DDR2 Memory Controller
16
0
45