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3.2.3
Configuring SDRAM Timing Registers (SDTIMR and SDTIMR2)
The SDRAM timing register (SDTIMR) and SDRAM timing register 2 (SDTIMR2) configure the DDR2
memory controller to meet the data sheet timing parameters of the attached DDR2 device. Each field in
SDTIMR and SDTIMR2 corresponds to a timing parameter in the DDR2 data sheet specification.
and
Table 20
display the register field name and corresponding DDR2 data sheet parameter name along
with the data sheet value. These tables also provide a formula to calculate the register field value and
displays the resulting calculation. Each of the equations include a minus 1 because the register fields are
defined in terms of DDR2 clock cycles minus 1. See
DDR2 Data
Register Field
Manual
Name
Parameter Name
T_RFC
t
RFC
T_RP
t
RP
T_RCD
t
RCD
T_WR
t
WR
T_RAS
t
RAS
T_RC
t
RC
T_RRD
t
RRD
T_WTR
t
WTR
Note:
The equation given above for the T_RRD field applies only for 8 bank DDR2 memories.
When interfacing to DDR2 memories with less than 8 banks, the T_RRD field should be
calculated using the following equation (t
DDR2 Data
Register Field
Manual
Name
Parameter Name Description
T_XSNR
t
XSNR
T_XSRD
t
XSRD
T_RTP
t
RTP
T_CKE
t
CKE
SPRUEM4A – November 2007
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Table 19. SDRAM Timing Register (SDTIMR) Configuration
Description
Refresh cycle time
Precharge command to 20
refresh or activate
command
Activate command to
read/write command
Write recovery time
Active to precharge
command
Activate to Activate
command in the same
bank
Activate to Activate
command in a different
bank
Write to read command 10
delay
Table 20. SDRAM Timing Register 2 (SDTIMR2) Configuration
Exit self refresh to a non-read
command
Exit self refresh to a read
command
Read to precharge command delay
CKE minimum pulse width
Section 4.4
and
Section 4.5
Data Manual
Formula
Value (nS)
(Register field must be )
127.5
(t
RFC
(t
f
RP
20
(t
RCD
15
(t
WR
45
(t
RAC
65
(t
f
RC
10
((4
t
RRD
(t
WTR
f
) - 1.
RRD
DDR2_CLK
Data Manual
Value
137.5 nS
200 (t
cycles)
CK
7.5 nS
3 (t
cycles)
CK
Supported Use Cases
Table 19
for more information.
Register
Value
f
) - 1
16
DDR2_CLK
) - 1
2
DDR2_CLK
f
) - 1
2
DDR2_CLK
f
) - 1
1
DDR2_CLK
f
) - 1
5
DDR2_CLK
) - 1
8
DDR2_CLK
) + (2
t
))/(4
t
) - 1 1
CK
CK
f
) - 1
1
DDR2_CLK
Formula (Register
Register
field must be )
Value
(t
f
) - 1
18
XSNR
DDR2_CLK
t
- 1
199
XSRD
(t
f
) - 1
1
RTP
DDR2_CLK
t
- 1
2
CKE
DDR2 Memory Controller
39
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