Lesson 2: Balancing Resources With Dual-Data Paths
Example 2–9. lesson2_c.asm
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SOFTWARE PIPELINE INFORMATION
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Loop Unroll Multiple
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Known Minimum Trip Count
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Known Maximum Trip Count
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Known Max Trip Count Factor
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Loop Carried Dependency Bound(^) : 0
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Unpartitioned Resource Bound
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Partitioned Resource Bound(*)
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Resource Partition:
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.L units
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.S units
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.D units
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.M units
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.X cross paths
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.T address paths
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Long read paths
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Long write paths
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Logical
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Addition ops (.LSD)
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Bound(.L .S .LS)
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Bound(.L .S .D .LS .LSD)
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Searching for software pipeline schedule at ...
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ii = 3
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done
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Epilog not entirely removed
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Collapsed epilog stages
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Prolog not entirely removed
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Collapsed prolog stages
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Minimum required memory pad : 8 bytes
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Minimum safe trip count
2-16
A–side
ops (.LS)
Schedule found with 5 iterations in parallel
Notice the following things in the feedback:
A schedule with three cycles (ii=3) : You can tell by looking at the .D units and
.T address paths that this 3–cycle loop comes after the loop has been unrolled
because the resources show a total of six memory accesses evenly balanced
between the A side and B side. Therefore, our new effective loop iteration inter-
val is 3/2 or 1.5 cycles.
A Known Minimum Trip Count of 10 : This is because we specified the count
of the original loop to be greater than or equal to twenty and a multiple of two
and after unrolling, this is cut in half. Also, a new line, Known Maximum Trip
: 2x
: 10
: 1073741823
: 1
: 3
: 3
B–side
0
0
2
1
3*
3*
2
2
1
1
3*
3*
1
1
0
0
1
1
(.L or .S unit)
0
1
(.L or .S or .D unit)
2
1
2
2
: 2
: 3
: 4
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