Texas Instruments TMS320C6000 Programmer's Manual page 34

Sometimes the compiler finds a valid software pipeline schedule but one or
more of the values is live too long. Lifetime of a register is determined by the
cycle a value is written into it and by the last cycle this value is read by another
instruction. By definition, a variable can never be live longer than the ii of the
loop, because the next iteration of the loop will overwrite that value before it
is read.
The compiler then proceeds to:
ii = 6 Did not find schedule
Sometimes, due to a complex loop or schedule, the compiler simply cannot
find a valid software pipeline schedule at a particular iteration interval.
Regs Live Always : 1/5 (A/B–side)
Max Regs Live : 14/19
Max Cond Regs Live : 1/0
Regs Live Always refers to the number of registers needed for variables
to be live every cycle in the loop. Data loaded into registers outside the
loop and read inside the loop will fall into this category.
Max Regs Live refers to the maximum number of variable live on any one
cycle in the loop. If there are 33 variables live on one of the cycles inside
the loop, a minimum of 33 registers is necessary and this will not be pos-
sible with the 32 registers available on the 'C62x and 'C67x cores. In addi-
tion, this is broken down between A and B side, so if there is uneven parti-
tioning with 30 values and there are 17 on one side and 13 on the other,
the same problem will exist. This situation does not apply to the 64 regis-
ters available on the 'C64x core.
Max Cond Regs Live tells us if there are too many conditional values
needed on a given cycle. The 'C62x and 'C67x cores have 2 A side and
3 B side condition registers available. The 'C64x core has 3 A side and 3
B side condition registers available.
After failing at ii = 6, the compiler proceeds to ii = 7:
ii = 7 Schedule found with 3 iterations in parallel
It is successful and finds a valid schedule with 3 iterations in parallel. This
means it is pipelined 3 deep. In other words, before iteration n has completed,
iterations n+1 and n+2 have begun.
Each time a particular iteration interval fails, the ii is increased and retried. This
continues until the ii is equal to the length of a list scheduled loop (no software
pipelining). This example shows two possible reasons that a loop was not soft-
ware pipelined. To view the full detail of all possible messages and their de-
scriptions, see Feedback Solutions in Appendix A.
Understanding Feedback
Introduction 1-15