Modulo Scheduling of Multicycle Loops
6.6.6.4 Scheduling the Remaining Instructions
Figure 6–14. Dependency Graph of Weighted Vector Sum (Scheduling ci +1)
.M1
.S1
pi_scaled
.L1X
.D1
mem
1
.L1
LOOP
Note:
Shaded numbers indicate the cycle in which the instruction is first scheduled.
6-70
Figure 6–14 shows the dependency graph with additional scheduling
changes. The final version of the loop, with all instructions scheduled correctly,
is shown in Table 6–15.
A side
LDW
0
.D1
ai_i+1
5
5
MPY
.M2
5
pi
2
SHR
.S2
7
1
ADD
ci
8
1
STH
9
SUB
cntr
5
1
B
6
B side
MPYHL
6
pi+1
2
SHR
9
pi+1_scaled
.L2
1
ADD
1
ci+1
.L2
1
STH
.D2
mem
LDW
.D2
bi_i+1
5
5 SHR
AND
7
.S2
bi
1
10
11
2
8
bi+1
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