Tms320C6000 Architecture; Tms320C6000 Pipeline - Texas Instruments TMS320C6000 Programmer's Manual

TMS320C6000 Architecture

TMS320C6000 Architecture / TMS320C6000 Pipeline
1.1 TMS320C6000 Architecture

1.2 TMS320C6000 Pipeline

1-2
The 'C62x is a fixed-point digital signal processor (DSP) and is the first DSP
to use the VelociTIt architecture. VelociTI is a high-performance, advanced
very-long-instruction-word (VLIW) architecture, making it an excellent choice
for multichannel, multifunctional, and performance-driven applications.
The 'C67x is a floating-point DSP with the same features. It is the second DSP
to use the VelociTIt architecture.
The 'C64x is a fixed-point DSP with the same features. It is the third DSP to
use the VelociTIt architecture.
The 'C6000 DSPs are based on the 'C6000 CPU, which consists of:
Program fetch unit
Instruction dispatch unit
Instruction decode unit
Two data paths, each with four functional units
Thirty-two 32-bit registers ('C62x and 'C67x)
Sixty-four 32-bit registers ('C64x)
Control registers
Control logic
Test, emulation, and interrupt logic
The 'C6000 pipeline has several features that provide optimum performance,
low cost, and simple programming.
Increased pipelining eliminates traditional architectural bottlenecks in pro-
gram fetch, data access, and multiply operations.
Pipeline control is simplified by eliminating pipeline locks.
The pipeline can dispatch eight parallel instructions every cycle.
Parallel instructions proceed simultaneously through the same pipeline
phases.