Texas Instruments TMS320C6000 Programmer's Manual page 204

6.6.6.2 Live Too Long
6.6.6.3 Solving the Live-Too-Long Problem
Scheduling SHR bi+1 on cycle 6 now creates a problem with scheduling the
ADD ci instruction. The parents of ADD ci (AND bi and SHR pi_scaled) are
scheduled on cycles 5 and 7, respectively. Because the SHR pi_scaled is
scheduled on cycle 7, the earliest you can schedule ADD ci is cycle 8.
However, in cycle 7, AND bi * writes bi for the next iteration of the loop, which
creates a scheduling problem with the ADD ci instruction. If you schedule
ADD ci on cycle 8, the ADD instruction reads the parent value of bi for the next
iteration, which is incorrect. The ADD ci demonstrates a live-too-long problem.
No value can be live in a register for more than the number of cycles in the loop.
Otherwise, iteration n + 1 writes into the register before iteration n has read that
register. Therefore, in a 2-cycle loop, a value is written to a register at the end
of cycle n, then all children of that value must read the register before the end
of cycle n + 2 .
The live-too-long problem in Table 6–13 means that the bi value would have
to be live from cycles 6–8, or 3 cycles. No loop variable can live longer than
the iteration interval, because a child would then read the parent value for the
next iteration.
To solve this problem move AND bi to cycle 6 so that you can schedule ADD ci
to read the correct value on cycle 8, as shown in Figure 6–13 and Table 6–14.
Optimizing Assembly Code via Linear Assembly
Modulo Scheduling of Multicycle Loops
6-67