Clock Distribution; Reset Management - SMART Embedded Computing PCIE-7217 Installation And Use Manual

Functional Description
3.12

Clock Distribution

Clocking for each CPU complex consists of two input crystals. One 24MHz crystal to drive
all the main buses and a 32.768kHz crystal to drive the real time clock. Processor clocks
are driven from the PCH device. Each CPU has a dual channel memory, each memory
channel provides an 1200MHz clock to their respective memory channel.
3.13

Reset Management

Each PCH reset is controlled by the CPLD. CPU and peripheral reset are controlled by the
PCH. During power up the CPLD state machine drives the reset control to each CPU during
an induced reset from the front panel reset switch.
For more information about Reset button, refer the section
58
Controls on page
PCIE-7217 Installation and Use (6806873A01B)
Functional Description
75.