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Table 4-4. PPC604-to-DRAM Timing — 50ns EDO Devices (Continued)
Access Type
4-Beat Read after Idle
(Quad-word misaligned)
4-Beat Read after 4-Beat Read
(Quad-word aligned)
4-Beat Read after 4-Beat Read
(misaligned)
4-Beat Write after Idle
4-Beat Write after 4-Beat Write
(Quad-word aligned)
1-Beat Read after Idle
1-Beat Read after 1-Beat Read
1-Beat Write after Idle
1-Beat Write after 1-Beat Write
Notes 1. These numbers assume that the PowerPC 604 bus master
Flash Memory
The MVME2300SC base board has provision for up to 5MB of Flash
memory.
4-9
Clock Periods Required for:
1st Beat
2nd Beat
8
1
5/2
1
4/2
4
1
4/3
8
1
7/5
4
1
9/7
is doing address pipelining with TS∗ occurring at the
minimum time after AACK∗ is asserted. Also the two
numbers shown in the 1st beat column are for page miss/page
hit.
2. In some cases, the numbers shown are averages and
specific instances may be longer or shorter.
General Description
3rd Beat
4th Beat
2
1
1
1
2
1
1
1
1
1
-
-
-
-
-
-
-
-
Total
Clocks
1
12
1
8/5
1
8/6
1
7
1
7/6
-
8
-
7/5
-
4
-
9/7
4
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