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PHB
physical address
PIB
PMC
POWER
PowerPC™
RAM
RAS
Raven
Reduced-Instruction-Set Computer (RISC)
RFI
ROM
RTC
SBC
GL-5
PCI Host Bridge
A binary address that refers to the actual location of information
stored in secondary storage.
PCI-to-ISA Bridge
PCI Mezzanine Card
Performance Optimized With Enhanced RISC architecture (IBM)
The trademark used to describe the Performance Optimized With
Enhanced RISC microprocessor architecture for Personal
Computers developed by the IBM Corporation. PowerPC is
superscalar, which means it can handle more than one instruction per
clock cycle. Instructions can be sent simultaneously to three types of
independent execution units (branch units, fixed-point units, and
floating-point units), where they can execute concurrently, but finish
out of order. PowerPC is used by Motorola, Inc. under license from
IBM.
Random-Access Memory. The temporary memory that a computer
uses to hold the instructions and data currently being worked with.
All data in RAM is lost when the computer is turned off.
Row Address Strobe. A clock signal used in dynamic RAMs to
control the input of the row addresses.
The PowerPC-to-PCI local bus bridge chip developed by Motorola
for the MVME2600 and MVME3600 series of boards. It provides
the necessary interface between the PowerPC 60x bus and the PCI
bus, and acts as interrupt controller.
A computer in which the processor's instruction set is limited to
constant-length instructions that can usually be executed in a single
clock cycle.
Radio Frequency Interference
Read-Only Memory
Real-Time Clock
Single Board Computer
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