I/O Implementation; Table 4-2. Power Requirements - Motorola MVME2300SC Series Installation And Use Manual

Functional Description
4
300MHz PowerPC 604

I/O Implementation

4-4
The Raven bridge controller ASIC provides the bridge between the
PowerPC microprocessor bus and the PCI local bus. Electrically, the
Raven chip is a 64-bit PCI connection. Four programmable map decoders
in each direction provide flexible addressing between the PowerPC
microprocessor bus and the PCI local bus.
The power requirements for the MVME2300SC are shown in

Table 4-2. Power Requirements

Configuration
4.5A typical
5.5A maximum
The MVME2300SC offers many standard features desirable in a computer
system — among them Ethernet and debug ports, Boot ROM, Flash
memory, DRAM, and an interface for two PCI Mezzanine Cards (PMCs)
— all contained in a one-slot VME package. Its flexible mezzanine
architecture allows relatively easy I/O upgrades.
There are four standard buses on the MVME2300SC:
PowerPC Processor Bus
PCI Local Bus
In addition, the MVME2300SC supplies connectivity from both PMC
slots to an SCSA (Signal Computing System Architecture) backplane
TDM bus, if the system supports one, via shared pins on VME connector
P2.
As shown in Figure 4-1, a Raven PCI Bridge ASIC provides the interface
from the Processor Bus to PCI. A W83C553 PCI/ISA Bridge (PIB)
Controller device performs the bridge function between PCI and ISA. The
Universe ASIC device provides the interface between the PCI Local Bus
and the VMEbus. A Falcon chipset is the ECC memory controller.
+5V Power +12V and –12V Power
PMC-dependent
(Refer to Appendix B)
Computer Group Literature Center Web Site
Table 4-2.
ISA Bus
VMEbus