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Analog Comparator
The Analog Comparator compares the input values on the positive input PB0 (AIN0) and negative input PB1 (AIN1). When
the voltage on the positive input PB0 (AIN0) is higher than the voltage on the negative input PB1 (AIN1), the Analog Com-
parator Output (ACO) is set (one). The comparator's output can trigger a separate interrupt, exclusive to the Analog
Comparator. The user can select interrupt triggering on comparator output rise, fall or toggle. A block diagram of the com-
parator and its surrounding logic is shown in Figure 26.
Figure 26. Analog Comparator Block Diagram.
INTERNAL
VOLTAGE
REFERENCE
(ATtiny12 ONLY)
Analog Comparator Control and Status Register – ACSR
Bit
7
$08
ACD
Read/Write
R/W
Initial value
0
Note:
AINBG is only available in ATtiny12.
•
Bit 7 - ACD: Analog Comparator Disable
When this bit is set (one), the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the
Analog Comparator. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE
bit in ACSR. Otherwise an interrupt can occur when the bit is changed.
•
Bit 6 - AINBG: Analog Comparator Bandgap Select in ATtiny12
In ATtiny12, when this bit is set, a fixed bandgap voltage of 1.22 ± 0.05V replaces the normal input to the positive input
(AIN0) of the comparator. When this bit is cleared, the normal input pin PB0 is applied to the positive input of the
comparator.
•
Bit 6- Res: Reserved bit in ATtiny10/11
This bit is a reserved bit in the ATtiny10/11 and will always read as zero.
•
Bit 5 - ACO: Analog Comparator Output
ACO is directly connected to the comparator output.
•
Bit 4 - ACI: Analog Comparator Interrupt Flag
This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog
Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to
the flag.
AINBG
MUX
6
5
4
(AINBG)
ACO
ACI
R(/W)
R
R/W
0
X
0
3
2
1
ACIE
-
ACIS1
R/W
R
R/W
0
0
0
ATtiny10/11/12
0
ACIS0
ACSR
R/W
0
35
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