Table Of Contents - Holtek HT32F52243 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52243/HT32F52253

Table of Contents

1 Introduction ........................................................................................................... 22
Overview .............................................................................................................................. 22
Features ............................................................................................................................... 23
Device Information ............................................................................................................... 27
Block Diagram ..................................................................................................................... 28
2 Document Conventions ....................................................................................... 29
3 System Architecture ............................................................................................. 30
Arm ® Cortex ® -M0+ Processor .............................................................................................. 30
Bus Architecture ................................................................................................................... 31
Memory Organization .......................................................................................................... 32
Memory Map ................................................................................................................................... 33
Embedded Flash Memory ............................................................................................................... 35
Embedded SRAM Memory ............................................................................................................. 35
AHB Peripherals ............................................................................................................................. 35
APB Peripherals ............................................................................................................................. 35
4 Flash Memory Controller (FMC) .......................................................................... 36
Introduction .......................................................................................................................... 36
Features ............................................................................................................................... 36
Functional Descriptions ....................................................................................................... 37
Flash Memory Map ......................................................................................................................... 37
Flash Memory Architecture ............................................................................................................. 38
Wait State Setting ........................................................................................................................... 38
Booting Configuration ..................................................................................................................... 39
Page Erase ..................................................................................................................................... 40
Mass Erase ..................................................................................................................................... 41
Word Programming ......................................................................................................................... 42
Option Byte Description .................................................................................................................. 43
Page Erase/Program Protection ..................................................................................................... 44
Security Protection .......................................................................................................................... 45
Register Map ....................................................................................................................... 46
Register Descriptions ........................................................................................................... 47
Flash Target Address Register - TADR .......................................................................................... 47
Flash Write Data Register - WRDR ............................................................................................... 48
Flash Operation Command Register - OCMR ............................................................................... 49
Flash Operation Control Register - OPCR ..................................................................................... 50
Flash Operation Interrupt Enable Register - OIER ........................................................................ 51
Flash Operation Interrupt and Status Register - OISR .................................................................. 52
Flash Page Erase/Program Protection Status Register - PPSR .................................................... 53
Flash Security Protection Status Register - CPSR ........................................................................ 54
Rev. 1.20 2 of 501 September 19, 2018