Holtek HT32F52243 User Manual page 9

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52243/HT32F52253
Output Stage ................................................................................................................................. 277
Update Management .................................................................................................................... 287
Single Pulse Mode ........................................................................................................................ 289
Asymmetric PWM Mode ............................................................................................................... 291
Timer Interconnection ................................................................................................................... 292
Trigger ADC Start.......................................................................................................................... 296
Lock Level Table ........................................................................................................................... 296
PDMA Request ............................................................................................................................. 297
Register Map ..................................................................................................................... 298
Register Descriptions ......................................................................................................... 299
Timer Counter Configuration Register - CNTCFR ....................................................................... 299
Timer Mode Configuration Register - MDCFR ............................................................................. 300
Timer Trigger Configuration Register - TRCFR ............................................................................ 303
Timer Control Register - CTR ...................................................................................................... 304
Channel 0 Input Configuration Register - CH0ICFR .................................................................... 305
Channel 1 Input Configuration Register - CH1ICFR .................................................................... 307
Channel 2 Input Configuration Register - CH2ICFR .................................................................... 309
Channel 3 Input Configuration Register - CH3ICFR .....................................................................311
Channel 0 Output Configuration Register - CH0OCFR ............................................................... 313
Channel 1 Output Configuration Register - CH1OCFR ............................................................... 315
Channel 2 Output Configuration Register - CH2OCFR ............................................................... 317
Channel 3 Output Configuration Register - CH3OCFR ............................................................... 319
Channel Control Register - CHCTR ............................................................................................. 321
Channel Polarity Configuration Register - CHPOLR .................................................................... 323
Channel Break Configuration Register - CHBRKCFR ................................................................. 324
Channel Break Control Register - CHBRKCTR ........................................................................... 325
Timer PDMA/Interrupt Control Register - DICTR ......................................................................... 327
Timer Event Generator Register - EVGR ..................................................................................... 329
Timer Interrupt Status Register - INTSR ...................................................................................... 331
Timer Counter Register - CNTR................................................................................................... 333
Timer Prescaler Register - PSCR ................................................................................................ 334
Timer Counter Reload Register - CRR ........................................................................................ 335
Timer Repetition Register - REPR ............................................................................................... 335
Channel 0 Capture/Compare Register - CH0CCR ...................................................................... 336
Channel 1 Capture/Compare Register - CH1CCR ...................................................................... 337
Channel 2 Capture/Compare Register - CH2CCR ...................................................................... 338
Channel 3 Capture/Compare Register - CH3CCR ...................................................................... 339
Channel 0 Asymmetric Compare Register - CH0ACR ................................................................. 340
Channel 1 Asymmetric Compare Register - CH1ACR ................................................................. 340
Channel 2 Asymmetric Compare Register - CH2ACR ................................................................. 341
Channel 3 Asymmetric Compare Register - CH3ACR ................................................................. 341
Rev. 1.20 9 of 501 September 19, 2018