Holtek HT32F52243 User Manual page 4

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52243/HT32F52253
AHB Configuration Register - AHBCFGR ...................................................................................... 87
AHB Clock Control Register - AHBCCR ........................................................................................ 88
APB Configuration Register - APBCFGR ....................................................................................... 90
APB Clock Control Register 0 - APBCCR0 .................................................................................... 91
APB Clock Control Register 1 - APBCCR1 .................................................................................... 92
Clock Source Status Register - CKST ........................................................................................... 94
APB Peripheral Clock Selection Register 0 - APBPCSR0 ............................................................. 95
APB Peripheral Clock Selection Register 1 - APBPCSR1 ............................................................. 97
HSI Control Register - HSICR ........................................................................................................ 99
HSI Auto Trimming Counter Register - HSIATCR ........................................................................ 100
MCU Debug Control Register - MCUDBGCR .............................................................................. 101
7 Reset Control Unit (RSTCU) .............................................................................. 104
Introduction ........................................................................................................................ 104
Functional Descriptions ..................................................................................................... 105
Power On Reset ........................................................................................................................... 105
System Reset ............................................................................................................................... 105
AHB and APB Unit Reset .............................................................................................................. 105
Register Map ..................................................................................................................... 106
Register Descriptions ......................................................................................................... 107
Global Reset Status Register - GRSR ......................................................................................... 107
AHB Peripheral Reset Register - AHBPRSTR ............................................................................. 108
APB Peripheral Reset Register 0 - APBPRSTR0 ........................................................................ 109
APB Peripheral Reset Register 1 - APBPRSTR1 .........................................................................110
8 General Purpose I/O (GPIO) ............................................................................... 112
Introduction ........................................................................................................................ 112
Features ............................................................................................................................. 113
Functional Descriptions ..................................................................................................... 113
Default GPIO Pin Configuration .....................................................................................................113
General Purpose I/O - GPIO .........................................................................................................113
GPIO Locking Mechanism .............................................................................................................115
Register Map ..................................................................................................................... 115
Register Descriptions ......................................................................................................... 116
Port A Data Direction Control Register - PADIRCR ......................................................................116
Port A Input Function Enable Control Register - PAINER .............................................................117
Port A Pull-Up Selection Register - PAPUR ..................................................................................118
Port A Pull-Down Selection Register - PAPDR .............................................................................119
Port A Open Drain Selection Register - PAODR .......................................................................... 120
Port A Output Current Drive Selection Register - PADRVR ......................................................... 121
Port A Lock Register - PALOCKR ................................................................................................ 122
Port A Data Input Register - PADINR ........................................................................................... 123
Port A Output Data Register - PADOUTR .................................................................................... 123
Port A Output Set/Reset Control Register - PASRR .................................................................... 124
Rev. 1.20 4 of 501 September 19, 2018