Altera SDI HSMC Reference Manual page 21

Chapter 2: Board Components
Clock Circuitry
Table 2–9. Audio Sample Rate versus Clock Frequency (Part 2 of 2)
Audio Sample Rate (kHz)
Table 2–10
S[2:0]. Outputs from CLK3 and CLK4 are not used in the VCXO PLL. The
frequencies programmed into the VCXO PLL support 4x and 5x over-sampling of the
most popular audio sample rates.
Table 2–10. VCXO PLL Frequency Output
© July 2009 Altera Corporation
Bit Rate Clock (MHz)
176.4
192
defines the frequency output with respect to the three 1-bit control signals,
S2 S1 S0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Oversampling Rate
22.5792
24.5760
CLK1 (MHz) CLK2 (MHz)
98.304 98.304
90.3168 90.3168
122.88 122.88
112.896 112.896
98.304 122.88
90.3168 112.896
98.304 90.3168
122.88 112.896
VCXO Frequency
5 112.8960
5 122.8800
CLK3 CLK4
OFF OFF
OFF OFF
OFF OFF
OFF OFF
OFF OFF
OFF OFF
OFF OFF
OFF OFF
SDI HSMC Reference Manual
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