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2–8
Figure 2–4. SDI Multi-Frequency VCXO Femto Clock Video PLL Block Diagram
CLK0
0
1
CLK1
CLK_SEL
SDI CLK
4
V3:V0
Master Reset
MR
MF
2
N1:N0
2
nBP1:nBP0
The clock control signals SDI_CLK_V[3:0] control the input divider for the first
translation stage of the SDI multi-frequency VCXO femto clock video PLL.
shows which frequency inputs lock to either 27 MHz or 26.973027 MHz crystals.
Various "P" and "M" preset divider options can be selected by adjusting the values to
produce a frequency of 27 MHz or the alternate frequency out of the VCXO. The "P"
divider divides the input frequency to the comparison frequency used by the phase
detector. The "M" divider divides the output frequency of the VCXO to the
comparison frequency used by the phase detector. After the VCXO is locked to
27 MHz (or alternate), the signal is then multiplied up to the output frequency by the
femto clock PLL (refer to
74.25 MHz, 54 MHz, or 36 MHz. The output frequency is set to 148.5 MHz for the
Altera reference design and most applications.
Table 2–5
femto clock video PLL.
SDI HSMC Reference Manual
Phase
Detector
VCXO Input
Pre-divider
+
–
(P Value from
Table 2-6)
VCXO PLL
Divider
Look-up Table
0
1
Table
lists the first frequency translation stage of the SDI multi-frequency VCXO
Loop
Filter
0
VCXO
Charge
Pump
VCXO Feedback Divider
(M Value from Table)
VCXO Jitter Attenuation PLL
01
Femto Clock
Frequency Multiplier
10
11
0 = x22
1 = x24
2–6). The output frequency can be 148.5 MHz,
Chapter 2: Board Components
Clock Circuitry
1
00
Output
Divider
01
10
00 = 4
11
01 = 8
10 = 12
11 = 18
Table 2–5
© July 2009 Altera Corporation
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