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Chapter 2: Board Components
Clock Circuitry
Figure 2–3. SDI HSMC Clocking Diagram
VSYNC
HSYNC
27.000 MHz
26.973 MHz
SDI HSMC CLK
PLL Settings
The SDI multi-frequency VCXO femto clock video PLL (ICS810001-21) is utilized for
the SDI reference clocks. The board inputs two crystals to the clock generator, a
27 MHz and 26.973027 MHz. The two frequencies allow low-jitter operation for US
and European SDI standard rates. The HSMC signal SDI_XTAL_SEL determines
which crystal is locked by the internal VCXO.
Clock inputs to the SDI PLL come from the HSMC host or through an SMA input.
Both inputs are end-terminated at 50 Ω to ground. The HSMC signal SDI_CLK_SEL
determines which input is active.
f
For more information on the SDI multi-frequency VCXO femto clock video PLL, refer
to the data sheet provided by IDT.
Figure 2–4
diagram.
© July 2009 Altera Corporation
Video Sync
Separator
Clock
EXT CLK IN
Generator
shows the SDI multi-frequency VCXO femto clock video PLL block
Video In
SDI CLK
Differential
Buffer
LF
2–7
EXTCLK_OUT (P)
EXTCLK_OUT (N)
SDI CLK (P)
SDI CLK (N)
SDI HSMC Reference Manual
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