Altera SDI HSMC Reference Manual page 17

Chapter 2: Board Components
Clock Circuitry
Table 2–5. First Frequency Translation Stage of the SDI Multi-Frequency VCXO Femto Clock Video PLL
VCXO PLL Divider Look-Up Table
V3:V0 Pins P Value
0000 1000
0010 1001
0010 11000
0011 11011
0100 11000
0101 4004
0110 4004
0111 1000
1000 250
1001 253
1010 92
1011 1
1100 1
1101 1
1110 1
1111 1
Table 2–6
VCXO femto clock video PLL.
Table 2–6. Second Frequency Translation Stage of the SDI Multi-Frequency VCXO Femto Clock Video PLL
Femto Clock Look-Up Table
MF, N1:N0 Pins FB Div
0,00 22
0,01 22
0,10 22
0,11 22
1,00 24
1,01 24
1,10 24
1,11 24
Table 2–7
video PLL.
© July 2009 Altera Corporation
Video Clock Application
M Value Input
1000 27 MHz
1000 27 MHz
4004 74.175 MHz
4000 74.25 MHz
4000 74.25 MHz
4004 27 MHz
4000 27 MHz
1001 26.973 MHz
91 74.175 MHz
92 74.25 MHz
92 27 MHz
600 45 kHz
(720P/60 hsync)
800 33.75 kHz
(1080l/60 hsync)
1728 15.625 kHz
(PAL hsync)
1716 15.734 kHz
(NTSC hsync)
960 28.125 kHz
(1080l/50 hsync)
lists the second frequency translation stage of the SDI multi-frequency
Video Clock Application
Out Div VCXO
4 27 MHz
8 27 MHz
12 —
18 —
4 —
8 —
12 27 MHz
18 27 MHz
shows the bypass function of the SDI multi-frequency VCXO femto clock
Alternate Video Clock Application
VCXO Input
27 MHz 26.973 MHz
26.973 MHz —
27 MHz —
26.973 MHz —
27 MHz —
27 MHz 26.973 MHz
26.973 MHz —
27 MHz —
27 MHz —
27 MHz —
27 MHz 26.973 MHz
27 MHz 44.955 kHz
(720P/59.94)
27 MHz 33.716 kHz
(1080l/59.94)
27 MHz —
27 MHz —
27 MHz —
Alternate Video Clock Application
Q
148.5 MHz 26.973 MHz
74.25 MHz 26.973 MHz
—
—
—
—
54 MHz
36 MHz
VCXO
26.973 MHz
—
—
—
—
26.973 MHz
—
—
—
—
26.973 MHz
26.973 MHz
26.973 MHz
—
—
—
VCXO Q
148.35 MHz
74.175 MHz
— —
— —
— —
— —
— —
— —
SDI HSMC Reference Manual
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