Altera SDI HSMC Reference Manual page 11

Chapter 2: Board Components
Board Overview
Table 2–1
Table 2–1. SDI HSMC Components (Part 1 of 2)
Board Reference
Devices
U1, U2 SDI cable tri-speed driver
U3 AES VCXO PLL
U4 Multi-format video sync
separator
U5 High frequency switching
regulator
U6 SDI multi-frequency VCXO
femto clock video PLL
U7 LVPECL differential clock
buffer
U8, U10 SDI cable equalizer
U9, U16 RS422 transceiver
U11, U12, U13 Linear regulator
U14, U15 Single gate tri-state buffer
SDI Inputs/Outputs
J1 SDI output channel 2
J8 SDI output channel 1
J2 SDI input channel 2
J9 SDI input channel 1
AES Inputs/Outputs
J3 AES output channel 1
J10 AES input channel 1
J14 AES output channel 2
J15 AES input channel 2
Clocks
J16 SMA SDI clock input
J17 SMA SDI clock output (P)
J18 SMA SDI clock output (N)
J12 SMA AES clock output
© July 2009 Altera Corporation
describes the components and lists their corresponding board references.
Name
Input signal to this driver is from the HSMC high-speed
serializer/deserializer (SERDES) section. The DC blocking caps are in
series with the connector and the integrated circuit (IC).
Programmed VCXO from Integrated Computer Solutions (ICS) to
produce frequencies of 98.304 MHz, 90.3168 MHz, 122.88 MHz, and
112.896 MHz.
Signals ODDEVEN, VFORMAT, VSYNC, HSYNC from this device are
available to the host board through the HSMC connector.
IC switching power supply configured for a 5 V output. The input
voltage is 12 V from the HSMC connector.
Low jitter femto clock, multi-crystal SDI video PLL.
Differential clock signals available at the SMA outputs and HSMC
connector.
Equalizes data transmitted over the cable.
Used as a differential line driver and receiver for the AES interface.
Regulator with an input of 5 V and output of 3.3 V.
For AES VCXO control.
Output is through a BNC connector driven from the SDI cable driver.
Output is through a BNC connector driven from the SDI cable driver.
The signal from this channel is input to a cable equalizer. This equalizer
can be bypassed.
The signal from this channel is input to a cable equalizer. This equalizer
can be bypassed.
Transformer-coupled output with 75-Ω driver impedance.
A 75-Ω transformer coupled with AES input channel.
Transformer-coupled output with 75-Ω driver impedance.
A 75-Ω transformer coupled with AES input channel.
This signal is input to the SDI clock PLL (CMOS). There is a 49.9-Ω
termination to ground at the pin.
An ECL compatible output. The ECL bias includes a 130-Ω pull-up to
3.3 V and a 82-Ω pull-down to ground.
An ECL compatible output. The ECL bias includes a 130-Ω pull-up to
3.3 V and a 82-Ω pull-down to ground.
This signal is output to the SMA AES clock (CMOS) and has a 33-Ω
series termination resistor.
Description
SDI HSMC Reference Manual
2–3