Altera SDI HSMC Reference Manual page 10

2–2
Figure 2–1. Top View of the SDI HSMC
SDI Output
Channel 2 (J1)
SDI Cable
Tri-speed Driver (U1)
SDI Output
Channel 1 (J8)
SDI Cable
Tri-speed Driver (U2)
AES VCXO PLL (U3)
SMA AES
Clock Output (J12)
High Frequency
Switching
Regulator (U5)
SMA SDI
Clock Input (J16)
Figure 2–2
Figure 2–2. Bottom View of the SDI HSMC (HSMC Connector View)
SDI Cable
Equalizer (U8)
RS422 Transceiver (U9)
SDI Cable
Equalizer (U10)
Linear Regulator (U11)
RS422 Transceiver (U16)
SDI HSMC Reference Manual
Equalizer Bypass Jumper (J5)
Carrier Detect — Mute Jumper (J4)
SDI
LVPECL
Multi-frequency
Differential
VCXO
Femto Clock
Video PLL (U6)
shows the bottom view of the SDI HSMC.
Carrier Detect — Mute Jumper (J6)
Equalizer Bypass Jumper (J7)
SMA SDI SMA SDI
Clock
Clock
Clock Output
Output
Buffer (N)
(P)
(J62) (J18)
(J17)
Linear Linear Single Gate
Regulator Tri-state
Regulator
(U12) (U13) Buffer (U14)
Chapter 2: Board Components
Board Overview
SDI Input
Channel 2 (J2)
AES Output
Channel 1 (J3)
SDI Input
Channel 1 (J9)
AES Input
Channel 1 (J10)
AES Output
Channel 2 (J14)
AES Input
Channel 2 (J15)
Multi-format Video
Sync Separator (U4)
HSMC
Connector (J19)
Single Gate
Tri-state
Buffer (U15)
© July 2009 Altera Corporation