Table of Contents
Advertisement
80C186EC 188EC 80L186EC 188EC
PCB
Function
Offset
00H
Master PIC Port 0
02H
Master PIC Port 1
04H
Slave PIC Port 0
06H
Slave PIC Port 1
08H
Reserved
0AH
SCU Int Req Ltch
0CH
DMA Int Req Ltch
0EH
TCU Int Req Ltch
10H
Reserved
12H
Reserved
14H
Reserved
16H
Reserved
18H
Reserved
1AH
Reserved
1CH
Reserved
1EH
Reserved
20H
WDT Reload High
22H
WDT Reload Low
24H
WDT Count High
26H
WDT Count Low
28H
WDT Clear
2AH
WDT Disable
2CH
Reserved
2EH
Reserved
30H
T0 Count
32H
T0 Compare A
34H
T0 Compare B
46H
T0 Control
38H
T1 Count
3AH
T1 Compare A
3CH
T1 Compare B
3EH
T1 Control
6
PCB
Function
Offset
40H
T2 Count
42H
T2 Compare
44H
Reserved
46H
T2 Control
48H
Port 3 Direction
4AH
Port 3 Pin State
4CH
Port 3 Mux Control
4EH
Port 3 Data Latch
50H
Port 1 Direction
52H
Port 1 Pin State
54H
Port 1 Mux Control
56H
Port 1 Data Latch
58H
Port 2 Direction
5AH
Port 2 Pin State
5CH
Port 2 Mux Control
5EH
Port 2 Data Latch
60H
SCU 0 Baud
62H
SCU 0 Count
64H
SCU 0 Control
66H
SCU 0 Status
68H
SCU 0 RBUF
6AH
SCU 0 TBUF
6CH
Reserved
6EH
Reserved
70H
SCU 1 Baud
72H
SCU 1 Count
74H
SCU 1 Control
76H
SCU 1 Status
78H
SCU 1 RBUF
7AH
SCU 1 TBUF
7CH
Reserved
7EH
Reserved
Figure 3 Peripheral Control Block Registers
PCB
Function
Offset
80H
GCS0 Start
82H
GCS0 Stop
84H
GCS1 Start
86H
GCS1 Stop
88H
GCS2 Start
8AH
GCS2 Stop
8CH
GCS3 Start
8EH
GCS3 Stop
90H
GCS4 Start
92H
GCS4 Stop
94H
GCS5 Start
96H
GCS5 Stop
98H
GCS6 Start
9AH
GCS6 Stop
9CH
GCS7 Start
9EH
GCS7 Stop
A0H
LCS Start
A2H
LCS Stop
A4H
UCS Start
A6H
UCS Stop
A8H
Relocation Register
AAH
Reserved
ACH
Reserved
AEH
Reserved
B0H
Refresh Base Addr
B2H
Refresh Time
B4H
Refresh Control
B6H
Refresh Address
B8H
Power Control
BAH
Reserved
BCH
Step ID
BEH
Powersave
PCB
Function
Offset
C0H
DMA 0 Source Low
C2H
DMA 0 Source High
C4H
DMA 0 Dest Low
C6H
DMA 0 Dest High
C8H
DMA 0 Count
CAH
DMA 0 Control
CCH
DMA Module Pri
CEH
DMA Halt
D0H
DMA 1 Source Low
D2H
DMA 1 Source High
D4H
DMA 1 Dest Low
D6H
DMA 1 Dest High
D8H
DMA 1 Count
DAH
DMA 1 Control
DCH
Reserved
DEH
Reserved
E0H
DMA 2 Source Low
E2H
DMA 2 Source High
E4H
DMA 2 Dest Low
E6H
DMA 2 Dest High
E8H
DMA 2 Count
EAH
DMA 2 Control
ECH
Reserved
EEH
Reserved
F0H
DMA 3 Source Low
F2H
DMA 3 Source High
F4H
DMA 3 Dest Low
F6H
DMA 3 Dest High
F8H
DMA 3 Count
FAH
DMA 3 Control
FCH
Reserved
FEH
Reserved
Advertisement
Table of Contents
