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Pin
Pin Name
Type
PEREQ
I
UCS
O
LCS
O
P1 0 GCS0
O
P1 1 GCS1
P1 2 GCS2
P1 3 GCS3
P1 4 GCS4
P1 5 GCS5
P1 6 GCS6
P1 7 GCS7
T0OUT
O
T1OUT
T0IN
I
T1IN
INT7 0
I
INTA
O
P3 5
I O
P3 4
P3 3 DMAI1
O
P3 2 DMAI0
NOTE
Pin names in parentheses apply to the 80C188EC 80L188EC
Table 2 Pin Descriptions (Continued)
Input
Output
Type
States
A(L)
Processor Extension REQuest signals that a data
transfer between an 80C187 Numerics Processor
Extension and Memory is pending Systems not using an
80C187 must tie this pin to V
on the 80C188EC 80L188EC
H(1)
Upper Chip Select will go active whenever the address of
a memory or I O bus cycle is within the address range
R(1)
programmed by the user After reset UCS is configured to
I(1)
be active for memory accesses between 0FFC00H and
P(1)
0FFFFFH
H(1)
Lower Chip Select will go active whenever the address of
a memory or I O bus cycle is within the address range
R(1)
programmed by the user LCS is inactive after a reset
I(1)
P(1)
H(X) H(1)
These pins provide a multiplexed function If enabled
each pin can provide a General purpose Chip Select
R(1)
output which will go active whenever the address of a
I(X) I(1)
memory or I O bus cycle is within the address limitations
P(X) P(1)
programmed by the user When not programmed as a
Chip-Select each pin may be used as a general purpose
output port
H(Q)
Timer OUTput pins can be programmed to provide single
clock or continuous waveform generation depending on
R(1)
the timer mode selected
I(Q)
P(X)
A(L)
Timer INput is used either as clock or control signals
depending on the timer mode selected This pin may be
A(E)
either level or edge sensitive depending on the
programming mode
A(L)
Maskable INTerrupt input will cause a vector to a specific
Type interrupt routine The INT6 0 pins can be used as
A(E)
cascade inputs from slave 8259A devices The INT pins
can be configured as level or edge sensitive
H(1)
INTerrupt Acknowledge output is a handshaking signal
used by external 82C59A Programmable Interrupt
R(1)
Controllers
I(1)
P(1)
A(L)
H(X)
Bidirectional open-drain port pins
R(Z)
I(X)
H(X)
H(X)
DMA Interrupt output goes active to indicate that the
channel has completed a transfer DMAI1 and DMAI0 are
R(0)
multiplexed with output only port functions
I(Q)
P(X)
80C186EC 188EC 80L186EC 188EC
Pin Description
This signal does not exist
SS
13
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