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Pin
Pin Name
Type
A18 S5
I O
A17 S4
A16 S3
(A15 8)
AD15 CAS2
I O
AD14 CAS1
AD13 CAS0
AD12 0
I O
(AD7 0)
S2 0
O
ALE
O
BHE
O
(RFSH)
NOTE
Pin names in parentheses apply to the 80C188EC 80L188EC
Table 2 Pin Descriptions (Continued)
Input
Output
Type
States
A(L)
H(Z)
These pins drive address information during the address
phase of the bus cycle During T2 and T3 these pins drive
R(WH)
status information (which is always 0 on the 80C186EC)
I(0)
These pins are used as inputs during factory test driving
P(0)
these pins low during reset will cause unspecified operation
On the 80C188EC A15 8 provide valid address information
for the entire bus cycle
S(L)
H(Z)
These pins are part of the multiplexed ADDRESS and DATA
bus During the address phase of the bus cycle address bits
R(Z)
15 through 13 are presented on these pins and can be
I(0)
latched using ALE Data information is transferred during the
P(0)
data phase of the bus cycle Pins AD15 13 CAS2 0 drive the
82C59 slave address information during interrupt
acknowledge cycles
S(L)
H(Z)
These pins provide a multiplexed ADDRESS and DATA bus
During the address phase of the bus cycle address bits 0
R(Z)
through 12 (0 through 7 on the 80C188EC) are presented on
I(0)
the bus and can be latched using ALE Data information is
P(0)
transferred during the data phase of the bus cycle
H(Z)
Bus cycle Status are encoded on these pins to provide bus
transaction information S2 0 are encoded as follows
R(1)
I(1)
P(1)
S2
0
0
0
0
1
1
1
1
H(0)
Address Latch Enable output is used to strobe address
information into a transparent type latch during the address
R(0)
phase of the bus cycle
I(0)
P(0)
H(Z)
Byte High Enable output to indicate that the bus cycle in
progress is transferring data over the upper half of the data
R(Z)
bus BHE and A0 have the following logical encoding
I(1)
P(1)
A0
0
0
1
1
On the 80C188EC 80L188EC RFSH is asserted low to
indicate a refresh bus cycle
80C186EC 188EC 80L186EC 188EC
Pin Description
S1
S0
Bus Cycle Initiated
0
0
Interrupt Acknowledge
0
1
Read I O
1
0
Write I O
1
1
Processor HALT
0
0
Instruction Queue Fetch
0
1
Read Memory
1
0
Write Memory
1
1
Passive (No bus activity)
Encoding (for 80C186EC
BHE
80L186EC only)
0
Word transfer
1
Even Byte transfer
0
Odd Byte transfer
1
Refresh operation
11
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