Intel 80C186EC Manual page 45

16-bit high-integration embedded processors
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80C186EC 188EC 80L186EC 188EC
272434 –19
NOTES
1 Address information is invalid If previous bus cycle was a read then the AD15 0 (AD7 0) lines will float during T1
Otherwise the AD15 0 (AD7 0) lines will continue to drive during T1 (data is invalid) All other control lines are in their
inactive state
2 All address lines drive zeros while in Powerdown or Idle Mode
Pin names in parentheses apply to 80C188EC 80L188EC
Figure 20 Halt Cycle Waveforms
45

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