Functional Block Diagram Of Dnr-12 Enclosure - UEi RACKtangle DNR-12-1G Series User Manual

PULLUPS
I/O
SLOTS
0..5, C
PWR
2.5V 3.3V, 24V
DNR-POWER-DC
© Copyright 2018
United Electronic Industries, Inc.
DNR-X-1G Series RACKtangle and HalfRACK Systems
The input current and all output voltages, including the +2.5, +3.3, and +24 VDC
from the NIC module, plus signals from the two temperature sensors mounted
within the enclosure, are input to a 24-bit delta-sigma A/D converter. Except for
Vin, the voltage sources use 1:23.1 dividers on the front end. Vin uses a 1:45.3
divider.
Figure 2-16 shows the interaction of modules within a DNR-12 enclosure when
the DNR-BUFFER module is used.
DATA BUS
CPU/NIC
ADDR/CTRL
DNR-BUFFER/
CLOCKS CLOCK DIST.
6
1.2V AND 1.5V
TEMP0
Figure 2-16. Functional Block Diagram of DNR-12 Enclosure
As shown above, the I/O slots are divided into two groups: 0 to 5 and 6 to 0xB.
0xC for the DC Power Module is included with the 0 to 5 group. The DNR-
BUFFER board is located at the center of the enclosure, which is also at the
center point of the ADDR/CTRL bus. The DNR-CPU-1000 module is also
located at the center of the enclosure and the center of the data bus to minimize
bus delays. The CPU addresses I/O Boards and transmits clock ticks through
the Buffer Board, which controls the Addr/Ctrl and clock lines to the modules.
Temperature sensors monitor temperatures within the enclosure above the
DNR-POWER-DC module and the DNR-CPU module.
October 2018
The DNR-12-1G Series RACKtangle System
2.5V,3.3V
TEMP1
ADDR/CTRL
CLOCKS
6
Chapter 2 20
PULLUPS
I/O
SLOTS
6...B
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