Back To Back Read, 32-Bit Address And Data - LSI LSI53C895A Technical Manual

Figure 6.19 Back to Back Read, 32-Bit Address and Data
CLK
(Driven by System)
GPIO0_FETCH/
)
(Driven by LSI53C895A
GPIO1_MASTER/
(Driven by LSI53C895A)
REQ/
(Driven by LSI53C895A)
GNT/
(Driven by Arbiter)
FRAME/
(Driven by LSI53C895A)
AD
(Driven by LSI53C895A-
Addr; Target-Data)
C_BE/
(Driven by LSI53C895A)
PAR
(Driven by LSI53C895A-
)
Addr; Target-Data
IRDY/
(Driven by LSI53C895A)
TRDY/
(Driven by Target)
STOP/
(Driven by Target)
DEVSEL/
(Driven by Target)
t
9
t
6
t
5
t
4
t
3
t
3
Data In
Addr
Out
t
3
CMD BE
t
3
Out
t
3
PCI and External Memory Interface Timing Diagrams
t
10
t
1
Addr
Out
t
2
CMD
t
1
In
t
2
t
1
t
2
t
1
t
2
Data In
BE
Out
In
6-27