LSI LSISAS1068 Technical Manual

Pci-x to 8-port serial attached scsi/sata controller

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TECHNICAL

MANUAL

LSISAS1068 PCI-X to

8-Port Serial Attached

SCSI/SATA Controller

F e b r u a r y 2 0 0 5

Version 2.0

DB14-000287-03

Table of Contents

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Summary of Contents for LSI LSISAS1068

Page 1 TECHNICAL MANUAL LSISAS1068 PCI-X to 8-Port Serial Attached SCSI/SATA Controller F e b r u a r y 2 0 0 5 Version 2.0 ® DB14-000287-03...
Page 2 LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties.
Page 3 This book is the primary reference and technical manual for the LSISAS1068 PCI-X to 8-Port Serial Attached SCSI/SATA Controller. It contains a complete functional description for the LSISAS1068, as well as the physical and electrical speciﬁcations for the LSISAS1068. Audience This document assumes that you are familiar with microprocessors and related support devices.
Page 4 (800) 433-5177; (503) 693-6232 (International); FAX (503) 693-8344 Serial ATA Working Group http://www.serialata.org Email: info@serialata.org Philips I C Bus Speciﬁcation http://www.semiconductors.philips.com SFF-8485 Serial GPIO Bus Speciﬁcation http://www.sffcommittee.org Preface Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 5 Preliminary Release. Modiﬁed text regarding IM and IS drive sup- port (page 1-4); identiﬁed throughout the Manual that the LSISAS1068 PCI interface is not tolerant of 5V PCI; corrected typo on page 3-2 regarding 636 Ball Grid Array; changed accu- racy requirement for Reference Clock signal to +/- 50ppm (Table 3.9);...
Page 7: Table Of Contents
Context RAM Fusion-MPT Architecture Overview PCI Functional Description 2.3.1 PCI Addressing 2.3.2 PCI Commands and Functions 2-11 2.3.3 PCI Arbitration 2-16 2.3.4 PCI Cache Mode 2-16 Contents Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 8 Power Signals 3-13 3.12 Power-On Sense Pins Description 3-15 3.13 Internal Pull-Ups and Pull-Downs 3-18 Chapter 4 PCI Host Register Description PCI Conﬁguration Space Register Description viii Contents Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 9 Reset and Interrupt Timing 5-10 External Memory Timing Diagrams 5-11 Pinout 5-17 Package Drawings 5-24 Appendix A Register Summary Appendix B Reference Speciﬁcations Index Customer Feedback Contents Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 11 NV Write, 1 NVAddrCs, 7 NVCSWidth, 2 NVWrRecover (Bytes Written as Selected by BEs 5-16 5.10 LSISAS1068 636 EPBGA-T Diagram (Top View) 5-23 5.11 JZ02-000015-00 (5Y) Mechanical Drawing 5-25 Contents Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 13 PCI Memory [1] Address Map 4-33 4.10 Interrupt Signal Routing 4-39 Absolute Maximum Stress Ratings Operating Conditions GigaBlaze Transmitter Voltage Characteristics—TX[7:0] GigaBlaze Receiver Voltage Characteristics—RX[7:0] GigaBlaze Transceiver Rise/Fall Characteristics—TX[7:0], Contents xiii Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 14: External Clock
Listing by Signal Name 5-17 5.27 Listing by Pin Number 5-20 LSISAS1068 PCI Conﬁguration Space Registers LSISAS1068 PCI I/O Space Registers LSISAS1068 PCI Memory [0] Space Registers Reference SpecifIcations Contents Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 15: Introduction
LSISAS1068 integrates eight high-performance SAS/SATA phys and a 64-bit, 133 MHz PCI-X bus master DMA core. Each of the eight phys on the LSISAS1068 is capable of 3.0 Gbit/s and 1.5 Gbit/s SAS link rates, and 3.0 Gbit/s and 1.5 Gbit/s SATA link rates. The LSISAS1068 supports the SAS protocol as described in the Serial Attached SCSI Standard, version 1.0, as well as SAS 1.1 features, such as support for the...
Page 16 ™ using the Gﬂx process technology. Each port on the LSISAS1068 supports SAS and SATA devices using the SAS Serial SCSI Protocol (SSP), Serial Management Protocol (SMP), Serial Tunneling Protocol (STP), and SATA. The SSP protocol enables communication with other SAS devices. SATA enables the LSISAS1068 to communicate with other SATA devices.
Page 17: Lsisas1068 Direct-Connect Example Application
LSISAS1068 Controller and LSISASx12 Expander Example Application PCI/PCI-X Interface 32-bit Memory Address/Data Flash ROM/ PSBRAM/ NVSRAM LSISAS1068 Interface LSISASx12 LSISASx12 SAS/SATA SAS/SATA SAS/SATA SAS/SATA Drives Drives Drives Drives General Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 18 I/Os and minimizes system bus overhead by coalescing interrupts. The Fusion-MPT architecture requires only a thin, easy to develop device drivers that is independent of the I/O bus. LSI Logic provides these device drivers. The LSISAS1068 supports a 32-bit external memory bus and a standard serial EEPROM interface.
Page 19: Benefits Of Sas
ATA master-slave architecture, while maintaining compatibility with existing ATA ﬁrmware. The LSISAS1068 can function as an SSP initiator, an SSP target, an SMP initiator, an STP initiator, or a SATA initiator. The LSISAS1068 uses SSP to communicate with other SAS devices, and uses SMP to communicate topology management information with other SAS devices.
Page 20: Benefits Of Pci-X
The Fusion-MPT architecture improves overall system performance by requiring only a thin device driver, which off loads the intensive work of managing I/Os from the system processor to the LSISAS1068. The use of thin, easy to develop, common OS device drivers accelerates time to market by reducing device driver development and certiﬁcation times.
Page 21: Benefits Of Gigablaze ® Transceivers
The LSISAS1068 supports up to a 133 MHz, 64-bit PCI-X bus and is backwards compatible with previous versions of the PCI/PCI-X speciﬁcation. Per the PCI-X addendum, the LSISAS1068 includes transaction information with all PCI-X transactions to enable more efﬁcient buffer management schemes.
Page 22: Summary Of Lsisas1068 Features
Summary of LSISAS1068 Features This section provides a summary of the LSISAS1068 features and beneﬁts. It contains information on Features, SATA Features, Performance, Integration, Usability, Flexibility, Reliability, and Testability. 1.6.1 SAS Features This section describes the SAS features. • Provides 8 fully independent phys •...
Page 23: Pci Performance
Supports the PCI Memory Write and Invalidate, Memory Read Line, and Memory Read Multiple commands • Supports the PCI-X Memory Read Dword, Split Completion, Memory Read Block, Memory Write Block commands Summary of LSISAS1068 Features Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 24: Integration
SRAM (PSBRAM) interface • Offers a ﬂexible programming interface to tune I/O performance • Allows mixed connections to SAS or SATA targets 1-10 Introduction Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 25: Reliability
• Offers JTAG boundary scan • Provides a UART interface for debugging • ® Offers ARM Multi-ICE for debugging the ARM966 processor Summary of LSISAS1068 Features 1-11 Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 27: Functional Description
Chapter 2 Functional Description This chapter provides a subsystem level overview of the LSISAS1068, a discussion of the Fusion-MPT architecture, and a functional description of the LSISAS1068 interfaces. This chapter contains the following sections: • Section 2.1, “Block Diagram Description”...
Page 28: Block Diagram Description
Block Diagram Description The LSISAS1068 consists of three major modules and a context RAM. The three major modules are the host interface module and the two Quad Port modules. The modules consist of the following components: • Host Interface Module –...
Page 29: Lsisas1068 Controller Block Diagram
DMA Arbiter Port Layer Connection Management and Switch SAS Link SAS Link SAS Link SAS Link SAS Phy SAS Phy SAS Phy SAS Phy Block Diagram Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 30: Host Interface Module Description
133 MHz PCI-X bus. The interface is backward compatible with previous implementations of the PCI speciﬁcation, with the exception that the LSISAS1068 does not support 5 V PCI. For more information on the PCI interface, refer to Section 2.3, “PCI Functional Description”.
Page 31 This block supports the LSISAS1068 LED and GPIO interfaces. There are a total of 17 LED signals on the LSISAS1068. Each of the eight phys has an LED signal to indicate activity on the link and an LED signal to indicate an error on the link.
Page 32: Quad Port
The UART provides test and debug access to the LSISAS1068. 2.1.2 Quad Port The Quad Port modules in the LSISAS1068 implement the SSP, SMP, and STP/SATA protocols, and manage the eight SAS/SATA phys. Each Quad Port module supports four SAS/SATA phys. The following subsections describe the Quad Port modules.
Page 33 2.1.2.5 SAS Link and Phy The LSISAS1068 uses the Gﬂx GigaBlaze transceivers to implement the SAS link. The SAS link layer manages SAS connections between initiator and target ports, data clocking, and CRC checking on received data. The SAS link is also responsible for starting a link reset sequence.
Page 34: Context Ram
LSISAS1068 hardware generates a maskable interrupt to the IOP, which can then read the doorbell value and take the appropriate action. When the IOP writes a value to the doorbell, the LSISAS1068 hardware generates a maskable interrupt to the host system. The host system can then read the doorbell value and take the appropriate action.
Page 35: Pci Functional Description
The host PCI interface complies with the PCI Local Bus Speciﬁcation, Version 3.0 and the PCI-X Addendum to the PCI Local Bus Speciﬁcation, Revision 2.0. The LSISAS1068 supports a 133 MHz, 64-bit PCI-X bus. The LSISAS1068 provides support for 64-bit addressing with Dual Address Cycle (DAC).
Page 36 IDSEL is not asserted. Bits AD[10:8] address the PCI Function Conﬁguration Space (AD[10:8] = 0b000). The LSISAS1068 does not respond to any other encodings of AD[10:8]. Bits AD[7:2] select one of the 64 Dword registers in the device’s PCI Conﬁguration Space.
Page 37: Pci Commands And Functions
Memory Write Block 1. The LSISAS1068 ignores reserved commands as a slave and never generates them as a master. 2. When acting as a slave in the PCI mode, the LSISAS1068 supports this command as the PCI Memory Read command.
Page 38 The following sections describe how the LSISAS1068 implements these commands. 2.3.2.1 Interrupt Acknowledge Command The LSISAS1068 ignores this command as a slave and never generates it as a master. 2.3.2.2 Special Cycle Command The LSISAS1068 ignores this command as a slave and never generates it as a master.
Page 39 The LSISAS1068 supports this command when operating in the PCI-X bus mode. 2.3.2.7 Memory Write Command The Memory Write command writes data to an agent mapped in the memory address space. The target assumes responsibility for data coherency when it returns “ready.”...
Page 40 Burst Size Selection – The Read Multiple command reads multiple cache lines of data during a single bus ownership. The number of cache lines the LSISAS1068 reads is a multiple of the cache line size, which Revision 3.0 of the PCI speciﬁcation provides. The LSISAS1068 selects the largest multiple of the cache line size based on the amount of data to transfer.
Page 41 Memory Read Line Command This command is identical to the Memory Read command except it additionally indicates that the master intends to fetch a complete cache line. The LSISAS1068 supports this command when operating in the PCI mode. 2.3.2.16 Memory Read Block Command The LSISAS1068 uses this command to read from memory.
Page 42: Pci Arbitration
LSISAS1068 selects the largest multiple of the cache line size based on the transfer size. When the DMA buffer contains less data than the value Cache Line Size register speciﬁes, the LSISAS1068 issues a Memory Write command on the next cache boundary to complete the data transfer.
Page 43: Power Management
SAS Functional Description The LSISAS1068 provides eight SAS/SATA phys. Each phy can form one side of the physical link in a connection with a phy on a different SAS/SATA device. The physical link contains four wires that form two differential signal pairs.
Page 44 3.0 Gbit/s SAS, increasing the number of phys in a port increases the data transfer rate. Combining four phys on the LSISAS1068 into a wide port enables bandwidths of up to 12.0 Gbits/s.
Page 45 Wide Port Wide Port Each phy on the LSISAS1068 can function as an SSP Initiator, an SSP target, an SMP initiator, an STP initiator, or a SATA Initiator. A phy can function in only one role during a connection, but function in different roles during different connections.
Page 46: External Memory Interface
AHB bus and an external 32-bit memory interface. This interface is for accessing external Flash ROM and NVSRAM devices. Because the LSISAS1068 uses a 32-bit multiplexed address/data bus, designs using the LSISAS1068 do not require latches or CPLD devices to construct memory addresses. 2.5.1...
Page 47: Flash Rom Controller
The LSISAS1068 Flash ROM interface provides access to nonvolatile code and parameter storage for both the embedded ARM core and the host system. An 8-bit wide Flash ROM is optional if the LSISAS1068 is not the boot device, and a suitable driver exists to initialize the LSISAS1068 and download its code.
Page 48: Flash Rom Block Diagram
The Fusion-MPT ﬁrmware for the LSISAS1068 supports all CFI Flash parts and a limited set of non-CFI Flash parts. Contact the LSI Logic or OEM representative for a current list of supported non-CFI Flash parts. Figure 2.5 provides a diagram of a Flash ROM conﬁguration.
Page 49: Nvsram Controller
4 bytes from the NVSRAM and returns the resulting 32-bit Dword for each AHB Dword read request Byte lane 3 of the LSISAS1068 external memory bus (MAD[31:24]) connects to the 8-bit data bus of the NVSRAM. BWE[2]/ provides the write enable signal for the NVSRAM.
Page 50: Serial Eeprom Interface
Vendor ID[15:0] Reserved PCI Unlock Reserved Device ID[15:0] Class Code[15:0] Reserved Reserved Reserved Class Code [23:16] Hardware Conﬁg [15:0] Reserved Reserved Option ROM Offset[23:0] Reserved 2-24 Functional Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 51: Zero Channel Raid
The ZCR_EN/ signal enables ZCR support on the LSISAS1068. Pulling ZCR_EN/ HIGH disables ZCR support on the LSISAS1068 and causes the LSISAS1068 to behave as a normal PCI-X to SAS controller. When ZCR is disabled, the ALT_GNT/ signal has no effect on the LSISAS1068 operation.
Page 52: Universal Asynchronous Receiver/Transmitter (Uart)
AD21 220 Ω AD19 Note: To maintain proper interrupt mapping, select the address line for use as IDSEL on the LSISAS1068 to be +2 address lines above IDSEL on ZCR slot. Universal Asynchronous Receiver/Transmitter (UART) The LSISAS1068 provides an industry standard UART interface. The...
Page 53: Multi-Ice Test Interface
ICE JTAG post. The header has a 100 mil spacing between posts. The connector is a 20-way header that mates with IDC sockets that are mounted on a ribbon cable. This header enables LSI Logic to debug the board design.
Page 55: Signal Description
Chapter 3 Signal Description This chapter describes the input and output signals of the LSISAS1068, and consists of the following sections: • Section 3.1, “Signal Organization” • Section 3.2, “PCI Signals” • Section 3.3, “PCI-Related Signals” • Section 3.4, “CompactPCI Signals”...
Page 56 Figure 5.11 page 5-25 provides a diagram of the LSISAS1068 636 Ball Grid Array (BGA). The following subsections provide the signal descriptions for the LSISAS1068. Signal Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 57: Lsisas1068 Functional Signal Grouping
JTAG and Test Interface TDI_ICE Interface TX[7:0]− TDO_ICE TX[7:0]+ TMS_ICE IDDTN SERIAL_CLK SERIAL_DATA PROCMON Communication ISTWI_CLK Interface SPARE[3:2] ISTWI_DATA ECC[5:2] UART_RX TST_RST/ UART_TX SCAN_ENABLE SCAN_MODE Signal Organization Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 58: Pci Signals
AF11, AF10, AA12, AF9, AD13, AF12, AE13, AB13, AC15, AF14, AD14, AB14, AB16, AC14 C_BE[7:0]/ AF19, AE17, AC17, AB15, AA6, AC9, AA11, AC12 AC11 PAR64 AE19 Signal Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 59: Pci Interface Control Signals
Refer to the PCI Local Bus Speciﬁcation, Version 3.0, and the PCI-X Addendum to the PCI Local Bus Speciﬁcation, SERR/ Version 2.0, for complete signal descriptions. PCI Signals Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 60: Pci Interrupt Signals
This signal provides the reference resistor node for the PCI-X impedance controller. BZVDD AA26 – This signal provides the reference resistor node for the PCI-X impedance controller. Signal Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 61: Compactpci Signals
A4, B4, A6, A9, A16, These signals are the Differential Transmitter signals for B18, A22, B22 each phy. TX[7:0]- A3, B5, A5, B9, A15, A18, A21, B23 CompactPCI Signals Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 62: Memory Interface Signals
The Multiplexed Address/Data Parity signals provide parity checking for MAD[31:0]. MADP[3] provides parity protection for the high-order byte (MAD[31:24]). while MADP[0] provides parity protection for low-order byte (MADP[7:0]). Signal Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 63: Communication Signals
C Data pin provides the I C data signal. UART_RX This signal is the UART Receive signal. UART_TX This signal is the UART Transmit signal. Communication Signals Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 64: Sio Signals
SIO_END_A, C24, The SIO module that currently controls the SIO SIO_END_B bus drives the Serial I/O End signal to end control of the bus. 3-10 Signal Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 65: Configuration And General Purpose Signals
IOP is operational. FSELA The Frequency Select signal supports clocking conﬁguration options for internal clocks. This signal is reserved for diagnostic purposes. Conﬁguration and General Purpose Signals 3-11 Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 66: 3.10 Jtag And Test Signals
SPARE[3:2] E22, G20 Reserved for LSI Logic factory test. RESERVED V4, W3 Reserved for LSI Logic factory test. These signals must be left unconnected. 3-12 Signal Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 67: 3.11 Power Signals
Y25, AA2, AA16, AA25, AB2, AB20, AB22, AB24, AC6, AC19, AD1, AD2, AD10, AD26, AE6, AE7, AE11, AE12, AE15, AE16, AE20, AE21, AF3, AF5, AF13, AF16, AF24 Power Signals 3-13 Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 68 C7, G10, F11, F13, G16, E17, F19, F21 TX_VSS[7:0] F7, F8, A7, E11, E14, D16, G18, TXB_VSS[7:0] D4, E8, F10, D11, F14, E16, B19, E20 3-14 Signal Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 69: 3.12 Power-On Sense Pins Description
Provide pull-up options for all MAD[31:0] bus signals. Pull all reserved MAD bus signals LOW. Table 3.16 describes the power-on sense options. Power-On Sense Pins Description 3-15 Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 70: Power-On Sense Pin Definitions
• MAD[29:17] – Reserved. • MAD[16], PCI-X Operation – Pulling this signal LOW enables the PCI-X operation. Pulling this signal HIGH disables PCI-X operation. 3-16 Signal Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 71 EEPROM. Pulling this signal LOW indicates of serial EEPROM size of 32 Kbits or 64 Kbits. Pulling this signal HIGH indicates a serial EEPROM size of 1 Kbit, 2 Kbits, 4 Kbits, 8 Kbits, or 16 Kbits. LSI Logic ﬁrmware requires 64 Kbits.
Page 72: 3.13 Internal Pull-Ups And Pull-Downs
ZCR_EN/ Internal Pull-up. CPCI_EN/ Internal Pull-up. CPCI_SWITCH Internal Pull-down. ISTWI_CLK, ISTWI_DATA H23, D24 Internal Pull-up. REFCLK_B Internal Pull-down. FSELA Internal Pull-down. TST_RST/ Internal Pull-up. 3-18 Signal Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 73: Pci Host Register Description
(Power Management, Messaged Signaled Interrupts, MSI-X, and PCI-X) to optimize device performance. The LSISAS1068 does not hard code the location and order of the PCI extended capability structures. The address and location of the PCI extended capability structures are subject to change. To access a PCI LSISAS1068 PCI-X to 8-Port Serial Attached SCSI/SATA Controller Version 2.0...
Page 74: Lsisas1068 Pci Configuration Space Address Map
MSI-X Table Offset 4-26 MSI-X PBA Offset 4-27 Reserved – PCI-X Command PCI-X Next Pointer PCI-X Capability ID 4-28 PCI-X Status 4-30 Reserved – PCI Host Register Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 75 The Command register provides coarse control over the PCI function’s ability to generate and respond to PCI cycles. Writing a zero to this register logically disconnects the LSISAS1068 PCI function from the PCI bus for all accesses except conﬁguration accesses.
Page 76 Setting this bit allows the PCI function to behave as a PCI bus master. Clearing this bit disables the PCI function from generating PCI bus master accesses. PCI Host Register Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 77 Received Master Abort (from Master) A master device sets this bit when a Master Abort command terminates its transaction (except for Special Cycle). PCI Conﬁguration Space Register Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 78 LSISAS1068 PCI function is not conﬁgured to operate at 66 MHz. Refer to Section 3.12, “Power-On Sense Pins Description,” more information. PCI Host Register Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 79 New Capabilities The LSISAS1068 PCI function sets this read only bit to indicate a list of PCI extended capabilities such as PCI Power Management, MSI, MSI-X, and PCI-X support. Interrupt Status This bit reﬂects the status of the INTA/ (or ALT_INTA/) signal.
Page 80 The Latency Timer register speciﬁes, in units of PCI bus clocks, the value of the Latency Timer for this PCI bus master. If the LSISAS1068 initializes in the PCI mode, the default value of this register is 0x00. If the LSISAS1068 initializes in the PCI-X mode, the default value of this reg- ister is 0x40.
Page 81 I/O Base Address This base address register maps the operating register set into I/O Space. The LSISAS1068 requires 256 bytes of I/O Space for this base address register. Hardware sets bit 0 to 0b1. Bit 1 is reserved and returns 0b0 on all reads.
Page 82 32 bits of the Memory Space [0] base address. The LSISAS1068 requires 1024 bytes of memory space. Memory [0] High [31:0] This ﬁeld contains the Memory [0] High address. 4-10 PCI Host Register Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 83 Memory Space [1] base address. Hardware programs bits [12:0] to 0b0000000000100, which indicates that the Memory Space [1] base address is 64 bits wide and that the memory data is not prefetchable. The LSISAS1068 requires 64 Kbytes of memory for Memory Space [1]. Memory [1] Low [31:0] This ﬁeld contains the Memory [1] Low address.
Page 84 (PCI-SIG). If the download from the EEPROM fails, this register contains 0x0000. If the serial EEPROM interface is disabled this register returns a value of 0x1000. 4-12 PCI Host Register Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 85 ID Control pin is pulled HIGH, this register contains 0x9000. Refer to Section 3.12, “Power-On Sense Pins Descrip- tion,” for additional information. PCI Conﬁguration Space Register Description 4-13 Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 86: Subsystem Id Register Download Conditions And Values
ROM. Note that to access the expansion ROM, the user must also set bit 1 in the PCI Command register. 4-14 PCI Host Register Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 87 Reserved Reserved [23:0] This register is reserved. Register: 0x38–0x3B Reserved 24 23 16 15 Reserved Reserved [31:0] This register is reserved. PCI Conﬁguration Space Register Description 4-15 Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 88 ALT_INTA/ pins. The Interrupt Request Routing Mode bits, bits [9:8] in the Host Interrupt Mask register, deter- mine if the function presents interrupts on INTA/, ALT_INTA/, or both. 4-16 PCI Host Register Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 89 This register speciﬁes the desired settings for the latency timer values in units of 0.25 µs. Min_Gnt speciﬁes how long of a burst period the device needs. The LSISAS1068 sets this register to 0x40 indicating a burst period of 16.0 µs.
Page 90 The PCI function clears this bit since no special initializa- tion is required before a generic class device driver can use it. Reserved This bit is reserved. 4-18 PCI Host Register Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 91 PME Clock The LSISAS1068 clears this bit since the chip does not provide a PME pin. Version [2:0] The PCI function programs these bits to 0b010 to indicate that the LSISAS1068 complies with the PCI Power Management Interface Speciﬁcation, Revision 1.2.
Page 92 MSI Capability ID [7:0] This register indicates the type of the current data structure. This register always returns 0x05, indicating Message Signaled Interrupts (MSI). 4-20 PCI Host Register Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 93 LSISAS1068. The host system software allocates all or a subset of the requested messages by writing to this ﬁeld. The number of allocated PCI Conﬁguration Space Register Description 4-21 Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 94: Multiple Message Enable Field Bit Encoding
ﬁeld to determine the number of requested messages. The number of requested messages must align to a power of two. The LSISAS1068 sets this ﬁeld to 0b000 to request one message. All other encodings of this ﬁeld are reserved.
Page 95 The host system software can program this register to 0x0000 to force the PCI function to generate 32-bit message addresses. PCI Conﬁguration Space Register Description 4-23 Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 96 For each Pending bit that is set, the function has a pend- ing associated message. Refer to the PCI speciﬁcation for a complete description of this register. 4-24 PCI Host Register Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 97 Setting this bit to mask interrupts on the INTA/ or ALT_INTA/ pins is a violation of the PCI speciﬁ- cation. PCI Conﬁguration Space Register Description 4-25 Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 98: Bir Field Definitions
BIR ﬁeld deﬁnitions. Table 4.4 BIR Field Deﬁnitions BIR Value Base Address Register 0x10 0x14 0x18 0x1C 0x20 0x24 Reserved Reserved 4-26 PCI Host Register Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 99 PCI-X Capability ID [7:0] This register indicates the type of the current data structure. This register returns 0x07, indicating the PCI-X Data Structure. PCI Conﬁguration Space Register Description 4-27 Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 100: Maximum Outstanding Split Transactions
ﬁeld. Table 4.5 Maximum Outstanding Split Transactions Bits [6:4] Maximum Outstanding Encoding Split Transactions 0b000 0b001 0b010 0b011 4-28 PCI Host Register Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 101: Maximum Memory Read Count
The host device driver sets this bit to allow the LSISAS1068 to attempt to recover from data parity errors. If the user clears this bit and the LSISAS1068 is operating in the PCI-X mode, the LSISAS1068 asserts SERR/ whenever the Master Data Parity Error bit in the Status register is set.
Page 102 This ﬁeld is reserved. Received Split Completion Error Message The LSISAS1068 sets this bit upon receipt of a split completion message if the split completion error attribute bit is set. Write a one (1) to this bit to clear it.
Page 103 LSISAS1068. The PCI function uses this number as part of its Requester ID and Completer ID. This ﬁeld is read for diagnostic purposes only. PCI Conﬁguration Space Register Description 4-31 Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 104 4-39 Reserved 0x0038–0x003F – Request Queue 0x0040 4-40 Reply Queue 0x0044 4-40 High Priority Request MFA Queue 0x0048 4-41 Reserved 0x004C–0x007F – 4-32 PCI Host Register Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 105 IOP processor and vice-versa. When a host system PCI master writes to the Host Registers->Doorbell register, the LSISAS1068 generates a maskable interrupt to the IOP. The value written by the host system is available for the IOP to read in the...
Page 106 Write Sequence register. The Diagnostic Write Enable bit, bit 7 in the Host Diagnostic register, indi- cates the write access status. 4-34 PCI Host Register Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 107 Reserved This ﬁeld is reserved. Diagnostic Write Enable The LSISAS1068 sets this read only bit when the host writes the correct Write I/O Key to the Write Sequence register. The LSISAS1068 clears this bit when the host writes a value other than the Write I/O Key to the...
Page 108 The number of signiﬁcant bits is determined by the size of the PCI Memory Space [1] in the serial EEPROM. Reserved [9:0] This ﬁeld is reserved. 4-36 PCI Host Register Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 109 24 23 16 15 Diagnostic Read/Write Data This register reads or writes Dword locations on the LSISAS1068 internal bus. This register is only accessible through PCI I/O Space and returns 0xFFFFFFFF if read through PCI Memory Space. The host can enable...
Page 110 PCI Host. A write to this register of any value clears the associated System Doorbell interrupt. IOP Doorbell Status The LSISAS1068 sets this bit when the IOP receives a message from the system doorbell but has yet to process it. The IOP processes the System Doorbell message then clears the corresponding system request interrupt.
Page 111: Interrupt Signal Routing
Setting this bit masks System Doorbell interrupts and prevents the assertion of a PCI interrupt for all System Doorbell interrupt conditions. PCI I/O Space and Memory Space Register Description 4-39 Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 112 Reply Free MFAs from the host system on writes. Reply FIFO [31:0] For reads, this register contains the Reply Post MFA. For writes, the register contains the Reply Free MFA. 4-40 PCI Host Register Description Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 113 The High Priority Request Queue accepts High Priority Request Post MFAs from the host on writes. The High Priority Request Post Queue is similar to the Request Post Queue, except that the LSISAS1068 processes requests from the High Priority Request Post FIFO before processing requests from the Request Post Queue.
Page 115 DC Characteristics This section of the manual describes the LSISAS1068 DC characteristics. Tables through 5.22 give current and voltage speciﬁcations. LSISAS1068 PCI-X to 8-Port Serial Attached SCSI/SATA Controller Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 116: Absolute Maximum Stress Ratings
These numbers are speciﬁed for the design of the I/O power network. Not all of the I supplied DD-I/O to the LSISAS1068 dissipates on-chip. LSI Logic recommends using a heat sink for the LSISAS1068. See the LSISAS1068 Design Con- siderations SEN for more detail. Speciﬁcations Version 2.0...
Page 117: Gigablaze Transmitter Voltage Characteristics-Tx[7:0]
SATA - 3.0 Gbit/s 66.6 - 136.6 psec For more information concerning the SAS/SATA Gigablaze transceivers, refer to the Serial Attached SCSI standard, version 1.0. DC Characteristics Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 118 0.9 × VDDIO = -500 µA – µA – Table 5.9 Inputs—ZCR_EN/, CPCI_EN/, TN/, UART_RX Parameter Unit VSS - 0.5 VDD + 0.3 µA µA pull-up Speciﬁcations Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 119 Schmitt Trigger Inputs—REFCLK_B, SIO_DIN_A, SIO_DIN_B Parameter Units – – Hysteresis – µA – µA pull-down Table 5.13 10 mA, 3-State Outputs—CPCI_LED/, HB_LED/ Parameter Unit – – µA DC Characteristics Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 120 NVSRAM_CS/ Parameter Unit – – µA Table 5.16 5 mA Outputs—UART_TX Parameter Unit – – µA Table 5.17 4 mA Outputs—PROCMON Parameter Unit – – µA Speciﬁcations Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 121 Table 5.20 5 mA Bidirectional Signals—SERIAL_CLK, SERIAL_DATA, ISTWI_CLK, ISTWI_DATA, GPIO[3:0], FAULT_LED[7:0]/, ACTIVE_LED[7:0]/ Parameter Unit VSS - 0.5 VDD + 0.3 – – µA µA pull-up DC Characteristics Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 122 – in_diff_pp – – µA – Table 5.22 Capacitance Capacitance Value 3.5 pF 3.5 pF (PCI-X pads) 5 pF Capacitance values do not include package capacitance. Speciﬁcations Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 123 For frequencies above 33 MHz, the clock frequency can not be changed beyond the spread spectrum limits except while RST/ is asserted. Duty cycle not to exceed 60/40. Figure 5.1 External Clock CLK, SCLK 1.4 V AC Characteristics Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 124 Table 5.25 Interrupt Output Symbol Parameter Units CLK HIGH to IRQ/ LOW CLK HIGH to IRQ/ HIGH IRQ/ deassertion time – Figure 5.3 Interrupt Output IRQ/ 5-10 Speciﬁcations Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 125: Flash Write, 1 Flashaddrcs, 7 Flashcswidth
A = AddressSetup, X = ReadRecovery Note: *Clock shown for reference. It is not part of the interface. External Memory Timing Diagrams 5-11 Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 126: Flash Read, 0 Flashaddrcs, 7 Flashcswidth
A = AddressSetup, I = Idle, R = Read, X = ReadRecovery Note: *Clock shown for reference. It is not part of the interface. 5-12 Speciﬁcations Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 127: Flash Read, 1 Flashaddrcs, 7 Flashcswidth
A = AddressSetup, I = Idle, R = Read, X = ReadRecovery, W = Wait Note: *Clock shown for reference. It is not part of the interface. External Memory Timing Diagrams 5-13 Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 128: Nv Read, 0 Nvaddrcs, 7 Nvcswidth, 1 Nvrdrecover
A = AddressSetup, I = Idle, R = Read, X = ReadRecovery Note: *Clock shown for reference. It is not part of the interface. 5-14 Speciﬁcations Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 129: Nv Read, 1 Nvaddrcs, 7 Nvcswidth, 2 Nvrdrecover
A = AddressSetup, I = Idle, R = Read, X = ReadRecovery, W = Wait Note: *Clock shown for reference. It is not part of the interface. External Memory Timing Diagrams 5-15 Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 130: Nv Write, 1 Nvaddrcs, 7 Nvcswidth, 2 Nvwrrecover
FLASH_CS/ and/or BWE2/. A = AddressSetup, I = Idle, X = WriteRecovery, W = Write Note: *Clock shown for reference. It is not part of the interface. 5-16 Speciﬁcations Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 131 AD[40] AC25 ECC3 MAD[24] 1. Pad locations marked N/C are not internally connected to the LSISAS1068 silicon. Pad locations marked RESERVED are for LSI Logic factory test use only. Refer to Section 3.10, “JTAG and Test Signals” to determine how to terminate the RESERVED pads.
Page 132 RTRIM SIO_DOUT_A TXB_VDD4 VDDIO33 1. Pad locations marked N/C are not internally connected to the LSISAS1068 silicon. Pad locations marked RESERVED are for LSI Logic factory test use only. Refer to Section 3.10, “JTAG and Test Signals” to determine how to terminate the RESERVED pads.
Page 133 VDDIO33 VDDIO33 VDDIO33 VDDIO33 1. Pad locations marked N/C are not internally connected to the LSISAS1068 silicon. Pad locations marked RESERVED are for LSI Logic factory test use only. Refer to Section 3.10, “JTAG and Test Signals” to determine how to terminate the RESERVED pads.
Page 134 MAD[9] TXB_VSS0 ACTIVE_LED[0]/ NVSRAM_CS/ 1. Pad locations marked N/C are not internally connected to the LSISAS1068 silicon. Pad locations marked RESERVED are for LSI Logic factory test use only. Refer to Section 3.10, “JTAG and Test Signals” to determine how to terminate the RESERVED pads.
Page 135 MAD[18] VDDIO33 VDDIO33 VDDIO33 1. Pad locations marked N/C are not internally connected to the LSISAS1068 silicon. Pad locations marked RESERVED are for LSI Logic factory test use only. Refer to Section 3.10, “JTAG and Test Signals” to determine how to terminate the RESERVED pads.
Page 136 AD[26] AC20 AD[59] AF25 1. Pad locations marked N/C are not internally connected to the LSISAS1068 silicon. Pad locations marked RESERVED are for LSI Logic factory test use only. Refer to Section 3.10, “JTAG and Test Signals” to determine how to terminate the RESERVED pads.
Page 138 Package Drawings The LSISAS1068 uses a 636 EPBGA-T package. The package code is Figure 5.11 provides the package drawing. 5-24 Speciﬁcations Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 139 Figure 5.11 JZ02-000015-00 (5Y) Mechanical Drawing (Sheet 1 of 3) Important: For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code 5Y. Package Drawings 5-25 Version 2.0...
Page 140 Figure 5.11 JZ02-000015-00 (5Y) Mechanical Drawing; Bottom View (Sheet 2 of 3) Important: For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code 5Y. 5-26 Speciﬁcations...
Page 141 Figure 5.11 JZ02-000015-00 (5Y) Mechanical Drawing; Bottom View (Sheet 3 of 3) Important: For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code 5Y. Package Drawings 5-27 Version 2.0...
Page 143 Memory [1] High 0x20–0x23 Read/Write 4-11 Reserved 0x24–0x27 Reserved 4-11 Reserved 0x28–0x2B Reserved 4-12 Subsystem Vendor ID 0x2C–0x2D Read Only 4-12 LSISAS1068 PCI-X to 8-Port Serial Attached SCSI/SATA Controller Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 144 MSI Mask Bits — Read/Write 4-24 MSI Pending Bits — Read Only 4-24 MSI-X Capability ID — Read Only 4-25 MSI-X Next Pointer — Read Only 4-25 Register Summary Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 145 Host Interrupt Mask 0x34 Read/Write 4-39 Reserved 0x38–0x3F Reserved – Request Queue 0x40 Read/Write 4-40 Reply Queue 0x44 Read/Write 4-40 High Priority Request MFA Queue 0x48 Read/Write 4-41 Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 146 0x34 Read/Write 4-39 Reserved 0x38–0x3F Reserved – Request Queue 0x40 Read/Write 4-40 Reply Queue 0x44 Read/Write 4-40 High Priority Request MFA Queue 0x48 Read/Write 4-41 Register Summary Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 147 Hot Plug PCI Speciﬁcation Microsoft PC2001 and Server 2001 Requirements – Microsoft Server Design Guide CIM Conﬁguration Management model – LSISAS1068 PCI-X to 8-Port Serial Attached SCSI/SATA Controller Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 149 4-39 arbitration 2-16 enable bus mastering ARM966E-S 1-4, 2-5, 4-35 enable I/O aux_current bit 4-18 LSISAS1068 PCI-X to 8-Port Serial Attached SCSI/SATA Controller IX-1 Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 150 2-16, scale bit 4-19 capabilities pointer register 4-15 select bit 4-19 capability ID DC characteristics MSI 4-20, 4-25 designed maximum cumulative read size bit 4-30 IX-2 Index Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 151 3-16, 3-17 write and invalidate bit expansion ROM base address expansion ROM base address register 4-14 Index IX-3 Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 152 2-11, 2-13, 2-15, 2-16 ISTW_CLK memory [0] high 4-5, 4-10 ISTW_DATA memory [0] low 4-5, 4-10 ISTWI_CLK 3-18 memory [1] high 4-5, 4-11 IX-4 Index Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 153 2-11, 2-12 memory read 2-11 memory read block 2-11, 2-13, 2-15 narrow port 2-18 memory read command 2-12 memory read dword 2-11 new capabilities bit Index IX-5 Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 154 [0] 2-4, 2-10, 4-30 memory space [1] 2-10, split completion command 2-11 memory write and invalidate command 2-11, split completion discarded bit 4-31 IX-6 Index Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 155 4-19 MSI mask bits 4-24 power-on reset 4-35 MSI message address 4-23 power-on sense pins 3-15 MSI message control 4-21 PROCMON 3-12, Index IX-7 Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 156 FIFO 2-4, 2-8, 4-38 ALT_GNT/ reply queue ALT_INTA/ reply queue register 4-40 BWE[3:0]/ REQ/ 3-5, 5-4, 5-5, 5-6, 5-7, BZR_SET REQ64/ 3-5, BZVDD request free FIFO C_BE[7:0]/ IX-8 Index Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 157 STOP/ 3-5, SERIAL_DATA STP 1-2, 2-19 SERR/ stress ratings STOP/ subsystem ID 4-14 3-12 subsystem ID configuration 3-16, 3-17 TCK_ICE 3-12 subsystem ID register 4-13 Index IX-9 Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 158 5-11 reset 5-10 timing diagrams 5-11 TMS 3-12, 3-18, TMS_ICE 3-12, 3-18, 3-18 3-12 TRDY/ 3-5, TRST/ 3-12, TRST_ICE/ 3-12, 3-18, TST_RST/ 3-11, 3-18, IX-10 Index Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Page 159 Thank you for your help in improving the quality of our documents. LSISAS1068 PCI-X to 8-Port Serial Attached SCSI/SATA Controller Version 2.0 Copyright © 2004 by LSI Logic Corporation. All rights reserved.
Page 160 LSI Logic Corporation Technical Publications M/S E-198 Fax: 408.433.4333 Please tell us how you rate this document: LSISAS1068 PCI-X to 8-Port Serial Attached SCSI/SATA Controller, Version 2.0. Place a check mark in the appropriate blank for each category. Excellent Good Average...

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