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LSI LSI53C1030 Technical Manual

Pci-x to dual channel ultra320 scsi multifunctio controller
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TECHNICAL
MANUAL
LSI53C1030 PCI-X to
Dual Channel Ultra320
SCSI Multifunction
Controller
J u n e 2 0 0 3
Version 2.1
®
DB14-000156-04

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  • Page 1 TECHNICAL MANUAL LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller J u n e 2 0 0 3 Version 2.1 ® DB14-000156-04...
  • Page 2 LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties.
  • Page 3 Chapter 4, PCI Host Register Description, provides a bit level description of the host register set of the LSI53C1030. LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 4 Englewood Cliffs, NJ 07632 (800) 947-7700 Ask for document number ISBN 0-13-796855-8, SCSI: Understanding the Small Computer System Interface SCSI Electronic Bulletin Board (719) 533-7950 Preface Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 5 Removed SCSI timing information from Chapter 5 and referred readers to the SCSI specification. Removed PSBRAM interface and all related information. Advance 2/2001 Initial release of document. Version 0.1 Preface Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 6 Preface Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 7: Table Of Contents

    PCI Commands and Functions 2.3.3 PCI Arbitration 2-15 2.3.4 PCI Cache Mode 2-15 2.3.5 PCI Interrupts 2-15 LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 8 Internal Pull-ups and Pull-downs 3-25 Chapter 4 PCI Host Register Description PCI Configuration Space Register Description PCI I/O Space and Memory Space Register Description 4-29 viii Contents Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 9 AC Characteristics External Memory Timing Diagrams 5-11 5.4.1 NVSRAM Timing 5-12 5.4.2 Flash ROM Timing 5-16 Package Drawings 5-20 Appendix A Register Summary Index Customer Feedback Contents Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 10 Contents Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 11 Flash ROM Write Cycle (Cont.) 5-19 5.12 LSI53C1030 456-Pin BGA Top View 5-22 5.12 LSI53C1030 456-Pin BGA Top View (Cont.) 5-23 5.13 456-Pin EPBGA (KY) Mechanical Drawing 5-28 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 12 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 13 Multiple Message Enable Field Bit Encoding 4-22 Maximum Outstanding Split Transactions 4-25 Maximum Memory Read Count 4-26 PCI I/O Space Address Map 4-30 PCI Memory [0] Address Map 4-30 xiii Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 14 NVSRAM Read Cycle Timing 5-12 5.17 NVSRAM Write Cycle 5-14 5.18 Flash ROM Read Cycle Timing 5-16 5.19 Flash ROM Write Cycle 5-18 LSI53C1030 PCI Registers Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 15 LSI53C1030 PCI I/O Space Registers LSI53C1030 PCI I/O Space Registers Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 16 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 17: Introduction

    Chapter 1 Introduction This chapter provides a general overview of the LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller. This chapter contains the following sections: • Section 1.1, “General Description” • Section 1.2, “Benefits of the Fusion-MPT Architecture” •...
  • Page 18 The LSI53C1030 is pin compatible with the LSI53C1010R PCI to Dual Channel Ultra160 SCSI Multifunction Controller to provide an easy and safe migration path to Ultra320 SCSI. The LSI53C1030 supports up to a 64-bit, 133 MHz PCI-X bus. The Ultra320 SCSI features for the...

  • Page 19: Typical Lsi53C1030 Board Application

    PCI-X Interface The LSI53C1030 integrates two high-performance SCSI Ultra320 cores and a 64-bit, 133 MHz PCI-X bus master DMA core. The LSI53C1030 employs three ARM966E-S processors to meet the data transfer flexibility requirements of the Ultra320 SCSI, PCI, and PCI-X ®...

  • Page 20: Typical Lsi53C1030 System Application

    Use the LSI Logic BIOS Configuration Utility or the IM DOS Configuration Utility to configure the IM firmware attributes. Using the LSI...

  • Page 21: Benefits Of The Fusion-Mpt Architecture

    LSI53C1030. Changes within the LSI53C1030 are transparent to the host device driver, operating system, and user. The Fusion-MPT architecture also saves the Benefits of the Fusion-MPT Architecture Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 22: Benefits Of Pci-X

    The LSI53C1030 supports up to a 133 MHz, 64-bit PCI-X bus and is backward compatible with previous versions of the PCI/PCI-X specification. The LSI53C1030 is a true multifunction PCI-X device and presents a single electrical load to the PCI bus.

  • Page 23: Benefits Of Surelink (Ultra320 Scsi Domain Validation)

    SPI-4 specifications. Domain validation verifies that the system is capable of transferring data at Ultra320 SCSI speeds, allowing the LSI53C1030 to renegotiate to a lower data transfer speed and bus width if necessary. SureLINK Domain Validation is the software control for the domain validation manageability enhancements in the LSI53C1030.

  • Page 24: Benefits Of Lvdlink Technology

    RC-type input filters. This improved driver and receiver technology helps ensure correct clocking of data. TolerANT input signal filtering is a built-in feature of the LSI53C1030 and all LSI Logic Fast SCSI, Ultra SCSI, Ultra2 SCSI, Ultra160 SCSI, and Ultra320 SCSI devices.

  • Page 25: Summary Of Lsi53C1030 Features

    Uses the Fusion-MPT (Message Passing Technology) drivers to provide support for Windows, Linux , Solaris , SCO Openserver, UnixWare , OpenUnix 8, and NetWare operating systems Summary of LSI53C1030 Features Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 26: Pci Performance

    Supports the PCI-X Memory Read Dword, Split Completion, Memory Read Block, and Memory Write Block commands • Supports up to 8 PCI-X outstanding split transactions • Supports Message Signalled Interrupts (MSI) 1-10 Introduction Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 27: Integration

    Receives 5.0 V PCI if the PCI5VBIAS pin connects to 5 V, but does not drive 5.0 V signals on the PCI bus Summary of LSI53C1030 Features 1-11 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 28: Reliability

    • Allows all SCSI signals to be accessed through programmed I/O • Supports JTAG boundary scan ® • Provides ARM Multi-ICE for debugging purposes 1-12 Introduction Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 29: Functional Description

    Chapter 2 Functional Description This chapter provides a subsytem level overview of the LSI53C1030, a discussion of the Fusion-MPT architecture, and a functional description of the LSI53C1030 interfaces. This chapter contains the following sections: • Section 2.1, “Block Diagram Description”...

  • Page 30: Block Diagram Description

    Two independent Ultra320 SCSI Channel Modules – Datapath Engine – Context Manager – Ultra320 SCSI Core Figure 2.1 illustrates the relationship between these modules. Functional Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 31: Host Interface Module Description

    It also supports the external memory, serial EEPROM, and General Purpose I/O (GPIO) interfaces. This section provides a detailed explanation of the host interface submodules. Block Diagram Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 32 2.1.1.1 PCI Interface The LSI53C1030 provides a PCI-X interface that supports up to a 64-bit, 133 MHz PCI-X bus. The interface is compatible with all previous implementations of the PCI specification. For more information on the PCI interface, refer to Section 2.3, “PCI Functional Description.”...
  • Page 33 40. The LSI53C1030 provides eight GPIO pins (GPIO[7:0]). These pins are under the control of the LSI53C1030 and default to the input mode upon PCI reset. The LSI53C1030 also provides three LED pins: A_LED/, B_LED/, and HB_LED/. Either firmware or hardware control A_LED/ and B_LED/.

  • Page 34: Scsi Channel Module Description

    Dword messages. When the host system writes to the doorbell, the LSI53C1030 hardware generates a maskable interrupt to the IOP, which can then read the doorbell value and take the appropriate action. When Functional Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 35: Pci Functional Description

    There are two 32-bit message queues: the request message queue and the reply message queue. The host uses the request queue to request an action by the LSI53C1030, and the LSI53C1030 uses the reply queue to return status information to the host. The request message queue consists of only the request post FIFO.

  • Page 36: Pci Addressing

    Dual Address Cycle (DAC). The LSI53C1030 is a true multifunction PCI-X device and presents a single electrical load to the PCI bus. The LSI53C1030 uses a single REQ/-GNT/ pair to arbitrate for PCI bus mastership. Separate interrupt signals for PCI Function [0] and PCI Function [1] allow independent control of the two PCI functions.

  • Page 37: Pci Commands And Functions

    LSI53C1030 must be Type 0. C_BE[3:0]/ address the individual bytes within each Dword and determine the type of access to perform. 2.3.1.2 PCI I/O Space The PCI specification defines I/O Space as a contiguous 32-bit I/O address that all system resources share, including the LSI53C1030. The...
  • Page 38 Memory Write Block 1. The LSI53C1030 ignores reserved commands as a slave and never generates them as a master. 2. When acting as a slave in the PCI mode, the LSI53C1030 supports this command as the PCI Mem- ory Read command.
  • Page 39 PCI or PCI-X bus mode. 2.3.2.5 Memory Read Command The LSI53C1030 uses the Memory Read command to read data from an agent mapped in the memory address space. The target can perform an anticipatory read if such a read produces no side effects. The LSI53C1030 supports this command when operating in the PCI bus mode.
  • Page 40 This command is reserved for future implementations of the PCI specification. The LSI53C1030 never generates this command as a master. When a slave, the LSI53C1030 supports this command using the Memory Read Block command. 2.3.2.9 Alias to Memory Write Block Command This command is reserved for future implementations of the PCI specification.
  • Page 41 Burst Size Selection – The Read Multiple command reads multiple cache lines of data during a single bus ownership. The number of cache lines the LSI53C1030 reads is a multiple of the cache line size, which Revision 2.2 of the PCI specification provides. The LSI53C1030 selects the largest multiple of the cache line size based on the amount of data to transfer.
  • Page 42 The PCI Local Bus specification states that the transfer size must be a multiple of the cache line size. The LSI53C1030 selects the largest multiple of the cache line size based on the transfer size. When the DMA buffer contains less data than the value...

  • Page 43: Pci Arbitration

    A pins (INTA/, ALT_INTA/) or the interrupt B pins (INTB/ or ALT_INTB/). If using MSI, the LSI53C1030 does not signal interrupts on INTx/ or ALT_INTx/. Note that enabling MSI to mask PCI interrupts is a violation of the PCI specification.

  • Page 44: Power Management

    State D2. The following sections describe the PCI Function power states in conjunction with each SCSI function. Power state actions are separate for each SCSI function. 2-16 Functional Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 45 2.3.6.1 Power State D0 Power State D0 is the maximum power state and is the power-up default state for each function. The LSI53C1030 is fully functional in this state. 2.3.6.2 Power State D1 Per the PCI Power Management Interface Specification, Power State D1 must have an equal or lower power level than Power State D0.

  • Page 46: Ultra320 Scsi Functional Description

    D0 cold cold by applying VCC and resetting the device. Placing a function in Power State D3 puts the LSI53C1030 core in the coma mode, clears the function’s PCI Command register, and continually asserts the function’s soft reset. Asserting soft reset clears all pending interrupts and 3-states the SCSI bus.
  • Page 47 Figure 2.2 provides a waveform diagram of paced data transfers and illustrates the use of the P1 line. Ultra320 SCSI Functional Description 2-19 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 48: Paced Transfer Example

    LSI53C1030 uses precompensation to adjust the strength of the REQ, ACK, parity, and data signals. When a signal transitions to HIGH or LOW, the LSI53C1030 boosts the signal drive strength for the first data transfer period, and then lowers the signal drive strength on the second data transfer period if the signal remains in the same state.

  • Page 49: Example Of Precompensation

    The number of bytes in an information unit transfer is always a multiple of four. If the number of bytes to transfer in the information unit is not a multiple of four, the LSI53C1030 transmits pad bytes to bring the byte count to a multiple of four.
  • Page 50 SPI-4 draft standard to determine the skew compensation. Depending on the state of the RTI bit in the PPR negotiation, the LSI53C1030 can either execute this training pattern during each connection, or can execute the training pattern, store the adjustment parameters, and recall them on subsequent connections with the given device.

  • Page 51: Scsi Bus Interface

    SCSI transfer rates. The A_DIFFSENS or B_DIFFSENS signals detect the different input voltages for HVD, LVD, and SE. The LSI53C1030 drivers are tolerant of HVD signal strengths, but do not support the HVD bus mode. The LSI53C1030 SCSI device 3-states its SCSI drivers when it detects an HVD signal level.

  • Page 52: External Memory Interface

    The LSI53C1030 provides Flash ROM, NVSRAM, and serial EEPROM interfaces. The Flash ROM interface stores the SCSI BIOS and firmware image. The Flash ROM is optional if the LSI53C1030 is not the boot device and a suitable driver exists to initialize the LSI53C1030.

  • Page 53: Flash Rom Block Diagram

    The first access to the Flash is a 16-byte burst read beginning at Flash address 0x000000. The LSI53C1030 compares the values read to the Flash signature values that Table 2.4 provides. If the signature values match, the LSI53C1030 performs the instruction located at Flash address 0x000000.

  • Page 54: Nvsram Interface

    MPT firmware is capable of maintaining a second disk as a mirror of the boot drive. To do so, the LSI Logic Fusion-MPT firmware writes to both the boot drive and the mirror drive. The mirroring of the boot drive is transparent to the BIOS, drivers, and operating system.

  • Page 55: Serial Eeprom Interface

    Table 2.5 provides the structure of the configuration record in the serial EEPROM. Serial EEPROM Interface 2-27 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 56: Zero Channel Raid

    LSI53C1030 responds to PCI configuration cycles when the IOPD_GNT/ and IDSEL signal are asserted. Connect the IOPD_GNT/ pin on the LSI53C1030 to the PCI GNT/ signal of the external I/O processor. This allows the I/O processor to perform PCI configuration...

  • Page 57: Zcr Circuit Diagram For Lsi53C1030 And Lsi53C1010R

    LSI53C1030 when the I/O processor is granted the PCI bus. This configuration also prevents the system processor from accessing the LSI53C1030 PCI configuration registers. LSI53C1030 based designs do not use the M66EN pin to determine the PCI bus speed.

  • Page 58: Multi-Ice Test Interface

    Multi-ICE Test Interface This section describes the LSI Logic requirements for the Multi-ICE test interface. LSI Logic recommends that all test signals be routed to a header on the board. The Multi-ICE test interface header is a 20-pin header for Multi-ICE debugging through the ICE JTAG port.

  • Page 59: Signal Description

    Chapter 3 Signal Description This chapter describes the input and output signals of the LSI53C1030. The chapter consists of the following sections: • Section 3.1, “Signal Organization” • Section 3.2, “PCI Bus Interface Signals” • Section 3.3, “PCI-Related Signals” •...

  • Page 60: Signal Organization

    LSI53C1030 456 Ball Grid Array (BGA). Table 5.20 Table 5.21 page 5-24 page 5-26 provide pinout listings for the LSI53C1030. Signal Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 61: Lsi53C1030 Functional Signal Grouping

    Memory MAD[15:0] PIPESTAT[2:0] Interface MADP[1:0] SCANEN MCLK SCANMODE MOE/ IDDTN RAMCE/ CLKMODE_0 SerialCLK CLKMODE_1 SerialDATA DIS_PCI_FSN/ DIS_SCSI_FSN/ ZCR_EN/ TESTACLK ZCR Interface IOPD_GNT/ TESTHCLK TESTCLKEN Signal Organization Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 62: Pci Bus Interface Signals

    Refer to the PCI Local Bus Specification, Version 2.2, and the PCI-X Addendum to the PCI Local Bus Specification, Version 1.0a, for this signal description. Signal Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 63: Pci Address And Data Signals

    Refer to the PCI Local Bus Specification, Version 2.2, and the PCI-X Addendum to the PCI Local Bus Specification, Version 1.0a, for this signal description. PCI Bus Interface Signals Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 64: Pci Interface Control Signals

    Refer to the PCI Local Bus Specification, Version 2.2, and the PCI-X Addendum to the PCI Local Bus Specification, Version 1.0a, for this signal description. Signal Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 65: Pci Arbitration Signals

    Refer to the PCI Local Bus Specification, Version 2.2, and the PCI-X Addendum to the PCI Local Bus Specification, Version 1.0a, for this signal description. PCI Bus Interface Signals Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 66: Pci Interrupt Signals

    INTB/ and/or ALT_INTB/. The interrupt request routing mode bits, bits [9:8] in the PCI Host Interrupt Mask register, control the routing of interrupt signals to INTB/ and/or ALT_INTB/. Signal Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 67: Pci-Related Signals

    INTB/ and/or ALT_INTB/. PVT2, PVT1 AF4, AE5 PVT2 and PVT1 provide biasing for PCI signals. Connect a 49.9 Ω, 1% resistor between PVT2 and PVT1. PCI-Related Signals Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 68: Scsi Interface Signals

    In the LVD mode, the negative and positive signals form the differential pair. In the SE mode, the negative signals represent the signal pin and the positive signals are a virtual ground. The LSI53C1030 does not support the HVD mode. If HVD signalling is present, the SCSI channel 3-states its drivers.
  • Page 69 HVD Mode: Driving this pin above 2.0 V (HIGH) indicates an HVD bus and causes SCSI Channel [0] to 3-state its SCSI drivers. SCSI Interface Signals 3-11 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 70: Scsi Channel [0] Control Signals

    SCSI Channel [0] Busy. A_SBSY+ A_SATN− SCSI Channel [0] Attention. A_SATN+ A_SRST− SCSI Channel [0] Bus Reset. A_SRST+ A_SSEL− SCSI Channel [0] Select. A_SSEL+ 3-12 Signal Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 71: Scsi Channel [1] Signals

    HVD Mode: Driving this pin above 2.0 V (high) indicates an HVD bus and causes SCSI Channel [1] to 3-state its SCSI drivers. SCSI Interface Signals 3-13 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 72: Memory Interface

    Flash ROM/NVSRAM Interface Pins Signal Name BGA Position Type Strength Description MCLK 4 mA Reserved. ADSC/ 4 mA Reserved. ADV/ 4 mA Reserved. 3-14 Signal Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 73 LOW Flash Address Latch Enable. For the Flash ROM, these signals provide clocks for address latches. For the NVSRAM, these signals provide the memory address strobe. Memory Interface 3-15 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 74: Zero Channel Raid Interface

    PCI configuration cycles if IOPD_GNT/ or IDSEL is asserted. Connect IOPD_GNT/ to PCI GNT/ on the external I/O processor. 3-16 Signal Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 75: Test Interface

    TRACEPKT[7:0] F4, G5, E3, C2, 8 mA Reserved. E4, F5, B2, D4 TRACESYNC 8 mA Reserved. PIPESTAT[2:0] C3, E6, D5 8 mA Reserved. Test Interface 3-17 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 76: Lsi Logic Test Pins

    TESTHCLK is for use only by LSI Logic. TN is for use only by LSI Logic. TESTCLKEN TESTCLKEN is for use only by LSI Logic. 3-18 Signal Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 77: Gpio And Led Signals

    HB_LED/ 12 mA Firmware blinks Heart Beat LED at a 1.0 second interval when the IOP is operational. GPIO and LED Signals 3-19 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 78: Power And Ground Pins

    No Connect. 1. To reduce signal noise that can affect FSN functionality, place a ferrite bead in series with the VDDA and VSSA pins. LSI Logic recommends a bead with a rating of 150 Ω at 100 MHz. 3-20 Signal Description Version 2.1...

  • Page 79: Power-On Sense Pins Description

    LOW or connect a 4.7 k Ω resistor between the appropriate pin and VDD to pull the pin HIGH. The LSI53C1030 samples these pins during PCI reset and holds their values upon the removal of PCI reset.
  • Page 80 • MAD[13], 66 MHz PCI – By default, internal logic pulls this pin LOW to enable 66 MHz PCI operation on the LSI53C1030 and to set the 66 MHz Capable bit in the PCI Status register. Pulling this pin HIGH...
  • Page 81 MAD[5:4], PCI Single/Multifunction and SCSI Single/Dual Channel Configuration – These pins work in conjunction with each other to configure the LSI53C1030 as a single function PCI-X to single channel SCSI controller or a multifunction PCI-X to dual channel SCSI controller. By default, hardware internally pulls MAD[5:4] down to configure the LSI53C1030 as multifunction PCI-X to dual channel SCSI controller.

  • Page 82: Pci-X Function To Scsi Channel Configurations

    Single Function PCI-X to Single Channel SCSI Controller • MAD[3], NVSRAM Select – By default, internal logic pulls this pin LOW, which has no effect on the LSI53C1030. Pulling this pin HIGH configures the external memory interface as an NVSRAM interface. •...

  • Page 83: Internal Pull-Ups And Pull-Downs

    Internal Pull-up. DIS_PCI_FSN/ Internal Pull-down. Pull up externally to enable correct operation of the PCI FSN. ZCR_EN/, IOPD_GNT/ N23, AC5 Internal Pull-up. Internal Pull-ups and Pull-downs 3-25 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 84 3-26 Signal Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 85: Pci Host Register Description

    Shading indicates a reserved bit or register. Do not access the reserved address areas. There are two PCI functions on the LSI53C1030. Each PCI function has its own independent interrupt pin and its own PCI Address space. The PCI System Address space consists of three regions: Configuration Space, Memory Space, and I/O Space.

  • Page 86: Lsi53C1030 Pci Configuration Space Address Map

    Message Upper Address 4-23 Message Data 4-24 Reserved – PCI-X Command PCI-X Next Pointer PCI-X Capability ID 4-25 PCI-X Status 4-27 Reserved – PCI Host Register Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 87 LSI53C1030 PCI function from the PCI bus for all accesses except configuration accesses. Reserved [15:9] This field is reserved. PCI Configuration Space Register Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 88 Space accesses. Enable I/O Space This bit controls the LSI53C1030 PCI function’s response to I/O Space accesses. Setting this bit enables the PCI PCI Host Register Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 89 DEVSEL/ for any bus command except Configuration Read and Configuration Write. The LSI53C1030 only PCI Configuration Space Register Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 90 PCI extended capabilities such as PCI Power Management, MSI, and PCI-X support. Reserved [3:0] This field is reserved. PCI Host Register Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 91 32-bit words. In the conventional PCI mode, the LSI53C1030 PCI function uses this register to determine whether to use Write and Invalidate or Write commands PCI Configuration Space Register Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 92 PCI device. If the LSI53C1030 is configured as a multifunction PCI device, bit 7 is set. If the LSI53C1030 is configured as a single function PCI device, bit 7 is cleared. PCI Host Register Description Version 2.1...
  • Page 93 I/O Base Address The I/O Base Address register maps the operating register set into I/O Space. The LSI53C1030 requires 256 bytes of I/O Space for this base address register. Hardware sets bit 0 to 0b1. Bit 1 is reserved and returns 0b0 on all reads.
  • Page 94 Memory [0] Low register map SCSI operating registers into Memory Space [0]. This register contains the upper 32 bits of the Memory Space [0] base address. The LSI53C1030 requires 1024 bytes of memory space. Memory [0] High [31:0] This field contains the Memory [0] High address.
  • Page 95 Memory Space [1] base address. Hardware programs bits [12:0] to 0b0000000000100, which indicates that the Memory Space [1] base address is 64 bits wide and that the memory data is not prefetchable. The LSI53C1030 requires 64 Kbytes of memory for Memory Space [1]. Memory [1] Low [31:0] This field contains the Memory [1] Low address.
  • Page 96 PCI Special Interest Group (PCI-SIG). By default, an internal pull-down on the MAD[7] Power-On Sense pin enables the serial 4-12 PCI Host Register Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 97 [15]. Table 4.2 lists the configuration options for the Power-On Sense pins and settings for this register. If the serial PCI Configuration Space Register Description 4-13 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 98: Subsystem Id Register Download Conditions And Values

    The least significant one (1) that remains repre- sents the binary version of the external memory size. For example, to indicate an external memory size of 32 4-14 PCI Host Register Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 99 Register: 0x35–0x37 Reserved Reserved Reserved [23:0] This register is reserved. PCI Configuration Space Register Description 4-15 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 100 The encoding of this read only register is unique to each function on the LSI53C1030. It indicates which interrupt pin the function uses. The value for Function [0] is 0x01, 4-16 PCI Host Register Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 101 The LSI53C1030 SCSI function sets this register to 0x06 since it requires the PCI bus every 1.5 µ s to maintain a data transfer rate of 320 Mbytes/s. PCI Configuration Space Register Description 4-17 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 102 Power Management Event (PME) pin. The LSI53C1030 clears these bits since the LSI53C1030 does not provide a PME signal. 4-18 PCI Host Register Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 103 Data_Scale [14:13] The PCI function clears these bits since the LSI53C1030 does not support the Power Management Data register. PCI Configuration Space Register Description 4-19 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 104 Power Management Bridge Support Extensions [7:0] This register indicates PCI Bridge specific functionality. The LSI53C1030 always returns 0x00 in this register. 4-20 PCI Host Register Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 105 This register points to the next item in the PCI function’s extended capabilities list. The value of this register varies according to system configuration. PCI Configuration Space Register Description 4-21 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 106: Multiple Message Enable Field Bit Encoding

    These read only bits indicate the number of messages that the LSI53C1030 requests from the host. The host system software reads this field to determine the number 4-22 PCI Host Register Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 107 Message Upper Address [31:0] The LSI53C1030 supports 64-bit MSI. This register con- tains the upper 32 bits of the 64-bit message address, PCI Configuration Space Register Description 4-23 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 108 [7:0] This register indicates the type of the current data struc- ture. This register returns 0x07, indicating the PCI-X Data Structure. 4-24 PCI Host Register Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 109 Table 4.4 Maximum Outstanding Split Transactions Bits [6:4] Maximum Outstanding Encoding Split Transactions 0b000 0b001 PCI Configuration Space Register Description 4-25 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 110: Maximum Outstanding Split Transactions

    The host device driver sets this bit to allow the LSI53C1030 to attempt to recover from data parity errors. If the user clears this bit and the LSI53C1030 is operating in the PCI-X mode, the LSI53C1030 asserts SERR/ whenever the Master Data Parity Error bit in the PCI Sta- register is set.
  • Page 111 This field is reserved. Received Split Completion Error Message The LSI53C1030 sets this bit upon receipt of a split com- pletion message if the split completion error attribute bit is set. Write a one (1) to this bit to clear it.
  • Page 112 Device Number [7:3] These read only bits indicate the device number of the LSI53C1030. This PCI function uses this number as part 4-28 PCI Host Register Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 113: Pci I/O Space And Memory Space Register Description

    Diagnostic Read/Write Address registers is only through PCI I/O Space. When the LSI53C1030 operates as a multifunction PCI device, the entire PCI Memory and PCI I/O Space register sets are visible to both PCI functions. When the LSI53C1030 operates as a single function PCI device, only PCI Function [0] register sets are accessible.

  • Page 114: Pci I/O Space Address Map

    PCI Memory [1] Address Map 0x0000– Diagnostic Memory 0x(Sizeof(Mem1) − 1) A bit level description of the PCI Memory and PCI I/O Spaces follows. 4-30 PCI Host Register Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 115 PCI function. When a host system PCI master writes to the Host Registers->Doorbell register, the LSI53C1030 generates a maskable interrupt to the IOP. The value written by the host system is available for the IOP to read in the System Interface Registers->Doorbell register.
  • Page 116 The LSI53C1030 sets this read only bit when the host writes the correct Write I/O Key to the Write Sequence register. The LSI53C1030 clears this bit when the host 4-32 PCI Host Register Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 117 PCI Memory Space [1]. Clearing this bit disables diagnostic memory accesses to PCI Memory Space [1] and returns 0xFFFF on reads. PCI I/O Space and Memory Space Register Description 4-33 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 118 Diagnostic Read/Write Data Read/Write Diagnostic Read/Write Data This register reads or writes Dword locations on the LSI53C1030 internal bus. This register is only accessible through PCI I/O Space and returns 0xFFFFFFFF if read through PCI Memory Space. The host can enable...
  • Page 119 This register holds the address that the Diagnostic Read/Write Data register writes data to or reads data from. PCI I/O Space and Memory Space Register Description 4-35 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 120 PCI interrupt when this bit is set and the cor- responding mask bit in the Host Interrupt Mask register is cleared. 4-36 PCI Host Register Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 121: Interrupt Signal Routing

    PCI interrupt for all reply interrupt condi- tions. Reserved [2:1] This field is reserved. PCI I/O Space and Memory Space Register Description 4-37 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 122 For reads, the Request Free MFA is empty and this reg- ister contains 0xFFFFFFFF. For writes, the register con- tains the Reply Free MFA. 4-38 PCI Host Register Description Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 123: Specifications

    This section of the manual describes the LSI53C1030 DC characteristics. Tables through 5.11 give current and voltage specifications. Figures are LVD transceiver schematics. LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller 5-1 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 124: Absolute Maximum Stress Ratings

    2. Core and analog supply only. The core voltage must come up before I/O voltage. The following equation must hold at all times: VDD_I/O ≤ (VDD_CORE + 2 V). Specifications Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 125: Lvd Driver

    LVD receiver voltage asserting Differential voltage |30| LVD receiver voltage negating Differential voltage 1. V = 0.7–1.8 V (Common Mode Voltage, nominal ~1.2 V.) DC Characteristics Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 126: Lvd Receiver

    – Guaranteed by design Input capacitance of PCI pads – Guaranteed by design Input capacitance of LVD pads – 6.5 pf pad 1.5 pf package Specifications Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 127: Ma Bidirectional Signals - Gpio[7:0], Mad[15:0], Madp[1:0]

    3.3 V PCI system is VDD. Refer to the signal description in Section 3.9, “Power and Ground Pins,” for more information concerning PCI5VBIAS. 2. Pull-down text does not apply to AD[31:0] and C_BE[3:0]/. DC Characteristics Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 128 Output high voltage Output low voltage 0.4 VDD 12 mA −10 µA 3-state leakage = 0 V, 3.6 V µA Pull current – – PULL-UP Specifications Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 129: Tolerant Technology Electrical Characteristics

    Output low current – = 0.5 V Short-circuit output high current – Short to V OSH2 Short-circuit output low current – Short to V TolerANT Technology Electrical Characteristics Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 130: Rise And Fall Time Test Condition

    3. Single pin only; irreversible damage can occur if sustained for longer than one second. Figure 5.3 Rise and Fall Time Test Condition 47 Ω 20 pF 2.5 V Specifications Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 131: Ac Characteristics

    1. For frequencies above 33 MHz, the clock frequency can not be changed beyond the spread spec- trum limits except while RST/ is asserted. 2. Duty cycle not to exceed 60/40. AC Characteristics Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 132: Reset Input

    Interrupt Output timing data. Table 5.15 Interrupt Output Symbol Parameter Units CLK HIGH to IRQ/ LOW CLK HIGH to IRQ/ HIGH IRQ/ deassertion time – 5-10 Specifications Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 133: External Memory Timing Diagrams

    Interrupt Output IRQ/ 5.4 External Memory Timing Diagrams This section provides timing diagrams and data for NVSRAM and Flash ROM timings. External Memory Timing Diagrams 5-11 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 134: Nvsram Timing

    MOE/ LOW to data clocked in – Data setup to MOE/ HIGH – Data setup to RAMCE/ HIGH – Data hold from RAMCE/ HIGH – 5-12 Specifications Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 135: Nvsram Read Cycle

    Data Driven by NVSRAM) FLSHALE1/ (Driven by LSI53C1030) FLSHALE0/ (Driven by LSI53C1030) RAMCE/ (Driven by LSI53C1030) MOE/ (Driven by LSI53C1030) BWE0/ (Driven by LSI53C1030) External Memory Timing Diagrams 5-13 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 136: Nvsram Write Cycle

    Address setup to BWE0/ LOW – RAMCE/ LOW to BWE0/ HIGH – RAMCE/ LOW to BWE0/ LOW – BWE0/ HIGH to RAMCE/ HIGH – RAMCE/ pulse width – 5-14 Specifications Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 137: Nvsram Write Cycle

    (Driven by LSI53C1030) FLSHALE1/ (Driven by LSI53C1030) FLSHALE0/ (Driven by LSI53C1030) RAMCE/ (Driven by LSI53C1030) MOE/ (Driven by LSI53C1030) BWE0/ (Driven by LSI53C1030) External Memory Timing Diagrams 5-15 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 138: Flash Rom Timing

    MOE/ LOW to data clocked in – Data setup to MOE/ HIGH – Data setup to FLSHCE/ HIGH – Data hold from FLSHCE/ HIGH – 5-16 Specifications Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 139: Flash Rom Read Cycle

    Data driven by Flash) FLSHALE1/ (Driven by LSI53C1030) FLSHALE0/ (Driven by LSI53C1030) FLSHCE/ (Driven by LSI53C1030) MOE/ (Driven by LSI53C1030) BWE0/ (Driven by LSI53C1030) External Memory Timing Diagrams 5-17 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 140: Flash Rom Write Cycle

    Address setup to BWE0/ LOW – FLSHCE/ LOW to BWE0/ HIGH – FLSHCE/ LOW to BWE0/ LOW – BWE0/ HIGH to RAMCE/ HIGH – FLSHCE/ pulse width – 5-18 Specifications Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 141: Flash Rom Write Cycle

    (Driven by LSI53C1030) FLSHALE1/ (Driven by LSI53C1030) FLSHALE0/ (Driven by LSI53C1030) FLSHCE/ (Driven by LSI53C1030) MOE/ (Driven by LSI53C1030) BWE0/ (Driven by LSI53C1030) External Memory Timing Diagrams 5-19 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 142: Package Drawings

    5.5 Package Drawings Figure 5.12 illustrates the signal locations on the Ball Grid Array (BGA). 5-20 Specifications Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 143 This page left blank intentionally. Package Drawings 5-21 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 144: Lsi53C1030 456-Pin Bga Top View

    INTB/ GNT/ AD31 AD29 AD26 AD25 AD21 AF10 AF11 AF12 AF13 VDD_IO VSS_IO TDI_CHIP PVT2 VDD_IO VSS_IO ALT_INTA/ AD30 VDD_IO VSS_IO AD20 PCI5VBIAS VDD_IO 5-22 Specifications Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 145: Lsi53C1030 456-Pin Bga Top View (Cont.)

    AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 VSS_IO VDDC AD19 VDD_IO VSS_IO AD10 VDD_IO VSS_IO VDD_IO VSS_IO Package Drawings 5-23 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 146 A_SD3+ B_SATN+ B_SREQ+ MAD0 AD41 A_SD4- B_SBSY- B_SRST- MAD1 AD42 A_SD4+ B_SBSY+ B_SRST+ MAD2 AD43 A_SD5- B_SCD- B_SSEL- MAD3 AD44 A_SD5+ B_SCD+ B_SSEL+ MAD4 5-24 Specifications Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 147 VSSC SerialDATA VDD_IO VSS_IO VSS_IO VSSC SERR/ AC17 VDD_IO VSS_IO VSS_IO VSSC STOP/ AB16 VDD_IO VSS_IO VSS_IO VSSC TCK_CHIP VDD_IO VSS_IO VSS_IO ZCR_EN/ Package Drawings 5-25 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 148 SCLK GPIO7 ZCR_EN/ B_SMSG- B_SD3- F4 TRACEPKT7 VSS_IO AD32 B_SSEL- B_SD5+ F5 TRACEPKT2 A_SMSG+ AD33 B_SREQ- B_SDP0- MAD9 A_SMSG- VDD_IO B_SD8+ B_SATN+ MAD1 VSS_IO 5-26 Specifications Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 149 AC10 PCI5VBIAS TMS_CHIP AF24 AD47 A_SD14- AC11 AD27 PVT1 AF25 VDD_IO AD46 A_SD13+ AC12 AD23 AE6 PCI5VBIAS AF26 VSS_IO VSS_IO TCK_ICE AC13 IDSEL INTB/ Package Drawings 5-27 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 150 5-28 Specifications Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

  • Page 151: Lsi53C1030 Pci Registers

    0x24–0x27; 0x28–0x2B Reserved 4-12 Subsystem Vendor ID 0x2C–0x2D Read Only 4-12 Subsystem ID 0x2E–0x2F Read Only 4-13 LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller A-1 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 152 Read/Write 4-27 1. The offset of the PCI extended capabilities registers can vary. Access these registers through the Next Pointer and Capability ID registers. Register Summary Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 153 Host Interrupt Status 0x30 Read/Write 4-36 Host Interrupt Mask 0x34 Read/Write 4-37 Reserved 0x38–0x3F Reserved – Request FIFO 0x40 Read/Write 4-38 Reply FIFO 0x44 Read/Write 4-38 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 154 Host Interrupt Status 0x30 Read/Write 4-36 Host Interrupt Mask 0x34 Read/Write 4-37 Reserved 0x38–0x3F Reserved – Request FIFO 0x40 Read/Write 4-38 Reply FIFO 0x44 Read/Write 4-38 Register Summary Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 155 2-23 memory [0] 4-10 AD[31:0] memory [1] 4-11 AD[63:0] BGA top view 5-22 address bidirectional signals LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller IX-1 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 156 4-28 4-29 reply interrupt 4-36 configuration reply interrupt mask 4-37 parameters 2-24 reset adapter 4-33 read command 2-10 2-12 2-13 reset history 4-32 4-33 IX-2 Index Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 157 5-11 diagnostic read/write data register 4-32 4-33 4-34 diagnostic read/write enable bit 4-33 ferrite bead 3-20 diagnostic write enable bit 4-32 4-35 fibre channel 1-11 IX-3 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 158 2-10 2-13 hot plug ALT_INTA/ 2-15 2-23 3-10 3-11 3-13 ALT_INTB/ 2-15 sense voltage coalescing 1-10 hysteresis doorbell mask bit 4-38 INTA/ 2-15 IX-4 Index Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 159 SCSI signals message control register 4-22 receiver voltage message data register 4-24 sense voltage message frame address 4-38 LVDlink 1-11 2-18 2-23 message passing technology IX-5 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 160 5-20 5-22 configuration record 2-28 packetized protocol 2-21 configuration space 2-27 packetized transfers 2-21 address map C_BE[3:0]/ PAR64 configuration write command 2-10 2-12 2-13 IX-6 Index Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 161 4-19 PCI_GNT/ 3-16 4-20 PCI5VBIAS 1-11 3-20 4-20 PCI-SIG 4-12 D1 support bit 4-19 PCI-X 1-10 1-11 4-20 133 MHz 3-21 D2 support bit 4-19 IX-7 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 162 4-37 diagnostic read/write address 4-35 reply message 2-15 4-38 diagnostic read/write data 4-34 reply message queue expansion ROM base address 4-14 IX-8 Index Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 163 3-10 signal descriptions clock 3-10 A_DIFFSENS 3-11 core A_LED/ 3-19 2-22 A_RBIAS 3-11 datapath engine A_SACK+- 3-12 domain validation 2-22 A_SATN+- 3-12 IX-9 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 164 INTA/ ZCR_EN/ 3-16 INTB/ signal drive strength 2-20 2-22 IOPD_GNT/ 3-16 signal list 5-24 5-26 IRDY/ signalled system error bit MAD[15:0] 3-15 3-21 signals IX-10 Index Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 165 2-28 3-22 3-23 4-14 TolerANT 1-12 subsystem ID register 4-13 TRACECLK 3-17 subsystem vendor ID 2-27 2-28 3-23 TRACEPKT[7:0] 3-17 subsystem vendor ID register 4-12 IX-11 Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 166 4-28 VDD_CORE VDD_IO 3-20 VDDA 3-20 VDDC 3-20 vendor ID register version bit 4-19 voltage analog common mode core feed-through protection 1-12 input IX-12 Index Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 167 Thank you for your help in improving the quality of our documents. LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
  • Page 168 Technical Publications M/S E-198 Fax: 408.433.4333 Please tell us how you rate this document: LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller Technical Manual, Ver- sion 2.1. Place a check mark in the appropriate blank for each category. Excellent Good Average...
  • Page 169 You can find a current list of our U.S. distributors, international distributors, and sales offices and design resource centers on our web site at http://www.lsilogic.com/contacts/index.html...

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