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4-40
REQ
SREQ/ Status
ACK
SACK/ Status
BSY
SBSY/ Status
SEL
SSEL/ Status
ATN
SATN/ Status
MSG
SMSG/ Status
C_D
SC_D/ Status
I_O
SI_O/ Status
Register: 0x0C
DMA Status (DSTAT)
Read Only
7
6
DFE
MDPE
1
0
Reading this register clears any bits that are set at the time the register
is read, but does not necessarily clear the register in case additional
interrupts are pending (the LSI53C895A stacks interrupts). The DIP bit
in the
Interrupt Status Zero (ISTAT0)
to mask DMA interrupt conditions individually through the
Enable (DIEN)
register.
When performing consecutive 8-bit reads of the DSTAT,
Status Zero (SIST0)
any order), insert a delay equivalent to 12 CLK periods between the
reads to ensure that the interrupts clear properly. See
"Functional Description,"
DFE
DMA FIFO Empty
This status bit is set when the DMA FIFO is empty. It is
possible to use it to determine if any data resides in the
FIFO when an error occurs and an interrupt is generated.
This bit is a pure status bit and does not cause an
interrupt.
Registers
5
4
BF
ABRT
SSI
0
0
register is also cleared. It is possible
and
SCSI Interrupt Status One (SIST1)
for more information on interrupts.
3
2
1
SIR
R
0
0
x
DMA Interrupt
SCSI Interrupt
Chapter 2,
7
6
5
4
3
2
1
0
0
IID
0
registers (in
7
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