LSI LSI53C1000 Technical Manual

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TECHNICAL

MANUAL

LSI53C1000

PCI to Ultra160

SCSI Controller

Version 2.1

F e b r u a r y 2 0 0 1

S14050.A

Table of Contents

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Summary of Contents for LSI LSI53C1000

Page 1 TECHNICAL MANUAL LSI53C1000 PCI to Ultra160 SCSI Controller Version 2.1 F e b r u a r y 2 0 0 1 ® S14050.A...
Page 2 LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties.
Page 3 Preface This book is the primary reference and technical manual for the LSI Logic LSI53C1000 PCI to Ultra160 SCSI Controller. This manual contains a complete functional description for the product and includes physical and electrical speciﬁcations. Audience This document was prepared for system designers and programmers who are using this device to design an Ultra160 SCSI port for PCI-based personal computers, workstations, servers or embedded applications.
Page 4 Prentice Hall 113 Sylvan Avenue Englewood Cliffs, NJ 07632 (800) 947-7700 Ask for document number ISBN 0-13-796855-8, SCSI: Understanding the Small Computer System Interface LSI Logic World Wide Web Home Page www.lsil.com SCSI SCRIPTS™ Processors Programming Guide, Order Number S14044.A Preface...
Page 5 Hexadecimal numbers are indicated by the preﬁx “0x” —for example, 0x32CF. Binary numbers are indicated by the preﬁx “0b” —for example, 0b0011.0010.1100.1111. Revision Record Revision Date Remarks 1/00 Advanced Version 5/00 Preliminary Version 11/00 Final Version. Changed branding from SYM53C1000 to LSI53C1000. 2/01 Changed Ultra3 references to Ultra160. Preface...
Page 6 Preface...
Page 7: Table Of Contents
Contents Chapter 1 Introduction General Description 1.1.1 New Features in the LSI53C1000 Beneﬁts of Ultra160 SCSI Beneﬁts of SureLINK (Ultra160 SCSI Domain Validation) Beneﬁts of LVDlink ® Beneﬁts of TolerANT Technology Summary of LSI53C1000 Beneﬁts 1.6.1 SCSI Performance 1.6.2 PCI Performance 1.6.3...
Page 8 2.5.3 Power State D2 2-64 2.5.4 Power State D3 2-64 Chapter 3 Signal Descriptions Signal Organization Internal Pull-ups and Pull-downs on LSI53C1000 Signals PCI Bus Interface Signals 3.3.1 System Signals 3.3.2 Address and Data Signals 3.3.3 Interface Control Signals 3.3.4 Arbitration Signals 3.3.5...
Page 9 Chapter 4 Registers PCI Conﬁguration Registers SCSI Registers 4-21 SCSI Shadow Registers 4-119 Chapter 5 SCSI SCRIPTS Instruction Set SCSI SCRIPTS 5.1.1 Sample Operation Block Move Instructions 5.2.1 First Dword 5.2.2 Second Dword 5-13 5.2.3 Third Dword 5-14 I/O Instructions 5-14 5.3.1 First Dword...
Page 10 Figures Typical LSI53C1000 Board Application Typical LSI53C1000 System Application LSI53C1000 Block Diagram DMA FIFO Sections 2-36 LSI53C1000 Host Interface SCSI Data Paths 2-37 Regulated Termination for Ultra160 SCSI 2-40 Determining the Synchronous Transfer Rate 2-45 Interrupt Routing Hardware Using the LSI53C1000...
Page 11 Read/Write Instruction - Second Dword 5-24 Transfer Control Instructions - First Dword 5-27 5.10 Transfer Control Instructions - Second Dword 5-33 5.11 Transfer Control Instructions - Third Dword 5-33 5.12 Memory Move Instructions - First Dword 5-35 5.13 Memory Move Instructions - Second Dword 5-36 5.14 Memory Move Instructions - Third Dword...
Page 12 6.39 Initiator and Target ST Synchronous Transfer 6-66 6.40 Initiator and Target DT Synchronous Transfer 6-69 6.41 LSI53C1000 329 BGA Chip - Top View 6-72 6.42 LSI53C1000 329 Ball Grid Array (Bottom view) 6-76 6.43 LSI53C1000 329 BGA Mechanical Drawing...
Page 13 Interface Control Signals Arbitration Signals Error Reporting Signals Interrupt Signals SCSI Bus Interface Signals SCSI Signals 3-10 3.10 SCSI Control Signals 3-12 3.11 GPIO Signals 3-13 3.12 Flash ROM and Memory Interface Signals 3-14 3.13 Test Interface Signals 3-15 3.14 Power and Ground Signals 3-16 3.15...
Page 14 6.11 Input Signals—CLK, GNT/, IDSEL, INT_DIR, RST/, SCLK, TCK, TDI, TEST_HSC, TEST_RST/, TEST_PD, TMS 6.12 8 mA Output Signals—INTA/, INTB/, ALT_INTA/, ALT_INTB/, REQ/, SERR/ 6.13 TolerANT Technology Electrical Characteristics for SE SCSI Signals 6.14 External Clock 6-11 6.15 Reset Input 6-12 6.16 Interrupt Output...
Page 15 80.0 Mbyte (16-Bit Transfers) Quadrupled 40 MHz Clock 6-68 6.50 Ultra160 SCSI Transfers 160.0 Mbyte (16-Bit Transfers) Quadrupled 40 MHz Clock 6-69 6.51 Alphanumeric list by Signal Names 6-74 6.52 Alphanumeric List by BGA Positions 6-75 LSI53C1000 PCI Register Map LSI53C1000 SCSI Register Map Contents...
Page 16 Contents...
Page 17: Chapter 1 Introduction
SCSI bus to any PCI system. The LSI53C1000 supports a 64-bit or 32-bit, 66 or 33 MHz PCI bus. The Ultra160 SCSI features implemented in the LSI53C1000 are: Double Transition (DT) clocking, Cyclic Redundancy Check (CRC), and Domain Validation.
Page 18 Three levels of Domain Validation are provided, assuring robust system operation. The LSI53C1000 has a local memory bus. This allows local storage of the device’s BIOS ROM in ﬂash memory or standard EPROMs. The LSI53C1000 supports programming of local ﬂash memory for BIOS updates.
Page 19: New Features In The Lsi53C1000
Typical PCI Computer System Architecture 1.1.1 New Features in the LSI53C1000 The LSI53C1000 is functionally similar to the LSI53C1010 PCI to Dual Channel Ultra160 SCSI Multifunction Controller, except that it implements a single SCSI function. Following is a list of LSI53C1000 features: •...
Page 20: Beneﬁts Of Ultra160 Scsi
Ultra160 SCSI performs 80 megatransfers per second (megatransfers/s) resulting in approximately double the synchronous data transfer rates of Ultra2 SCSI. The LSI53C1000 performs 16-bit, Ultra160 SCSI synchronous data transfers as fast as 160 Mbytes/s. This advantage is most noticeable in heavily loaded systems, or large block size applications such as video on-demand and image processing.
Page 21: Beneﬁts Of Surelink (Ultra160 Scsi Domain Validation)
AIP is also supported by the LSI53C1000, protecting all nondata phases, including command, status, and messages. CRC, along with AIP, provides end-to-end protection of the SCSI I/O. SureLINK Domain Validation provides 3 levels of integrity checking: Basic (level 1), Enhanced (level 2), and Margined (level 3). Further information on SureLINK is available in Section 1.3, “Beneﬁts of...
Page 22: Beneﬁts Of Lvdlink
For backward compatibility to existing SE devices, the LSI53C1000 features universal LVDlink transceivers that support LVD SCSI and SE SCSI. This allows use of the LSI53C1000 in both legacy and Ultra160 SCSI applications. ® 1.5 Beneﬁts of TolerANT...
Page 23: Summary Of Lsi53C1000 Beneﬁts
SCSI operations. TolerANT input signal ﬁltering is a built-in feature of the LSI53C1000 and all LSI Logic Fast SCSI, Ultra SCSI, Ultra2 SCSI, and Ultra160 SCSI devices. The beneﬁts of TolerANT technology include increased noise immunity when the signal transitions to HIGH, better performance due to balanced duty cycles, and improved fast SCSI transfer rates.
Page 24 – LVDlink transceivers save the cost of external differential transceivers. – Supports a long-term performance migration path. • Bursts of up to 512 bytes across the PCI bus with an independent 896–920 byte FIFO. • Handles phase mismatches in SCRIPTS without interrupting the system processor.
Page 25: Pci Performance
• Complies with PCI Bus Power Management Speciﬁcation, Revision 1.1. • Complies with PC99. 1.6.3 Integration The following features ease integration of the LSI53C1000 into a system. • Ultra160 SCSI PCI Controller. • Integrated LVD transceivers. • Full 32-bit or 64-bit PCI DMA bus master.
Page 26: Ease Of Use
1.6.4 Ease of Use The following features of the LSI53C1000 make the device user friendly. • Up to 1 Mbyte of add-in memory support for BIOS and SCRIPTS storage. • Reduced SCSI development effort. • Compiler-compatible with existing LSI53C7XX and LSI53C8XX family SCRIPTS.
Page 27: Reliability
Selectable INT pin disable bit. • Compatible with 3.3 V and 5 V PCI. 1.6.6 Reliability The following features enhance the reliability of the LSI53C1000: • CRC and AIP provide end-to-end SCSI I/O protection. • 2 kV ESD protection on SCSI signals.
Page 28 1-12 Introduction...
Page 29: Chapter 2 Functional Description
Chapter 2 Functional Description This chapter provides a functional description of the LSI53C1000. This chapter is divided into the following sections: • Section 2.1, “PCI Functional Description” • Section 2.2, “SCSI Functional Description” • Section 2.3, “Parallel ROM Interface” •...
Page 30: Lsi53C1000 Block Diagram
Drivers and Receivers JTAG Ultra160 JTAG ROM/Flash 2 Wire Serial SCSI Bus Memory EEPROM Bus The LSI53C1000 has a wide Ultra160 SCSI channel. The SCSI channel incorporates an independent DMA FIFO and a separate internal 8 KByte SCRIPTS RAM. Functional Description...
Page 31: Pci Functional Description
PCI Conﬁguration Register Map. At initialization time, each PCI device is assigned a base address for memory and I/O accesses. In the LSI53C1000, the upper 24 bits of the address are selected. On every access, the LSI53C1000 compares its assigned base addresses with the value on the Address/Data bus during the PCI address phase.
Page 32: Pci Bus Commands And Functions Supported
2.1.1.2 I/O Space The PCI speciﬁcation deﬁnes I/O space as a contiguous 32-bit I/O address that is shared by all system resources, including the LSI53C1000. Base Address Register Zero (BAR0) (I/O) determines which 256-byte I/O area this device occupies. 2.1.1.3 Memory Space The PCI speciﬁcation deﬁnes memory space as a contiguous 64-bit...
Page 33 Chip Test Three (CTEST3) register. 2.1.2.1 Interrupt Acknowledge Command The LSI53C1000 does not respond to this command as a slave and it never generates this command as a master. 2.1.2.2 Special Cycle Command The LSI53C1000 does not respond to this command as a slave and it never generates this command as a master.
Page 34 The given bus encoding is reserved. 2.1.2.6 Memory Read Command The LSI53C1000 uses the Memory Read command to read data from an agent mapped in the Memory Address Space. The target may perform an anticipatory read if such a read produces no side effects.
Page 35 Chip Test Five (CTEST5) register, bit 2. 2.1.2.11 Dual Address Cycles (DAC) Command When 64-bit addressing is required, the LSI53C1000 performs DAC, per the PCI 2.2 speciﬁcation. If any of the selector registers contain a nonzero value, a DAC is generated.
Page 36 The Read Line function in the LSI53C1000 takes advantage of the PCI 2.2 speciﬁcation regarding issuance of this command. If the cache mode is disabled, no Read Line commands are issued.
Page 37 • The chip is aligned to a cache line boundary. When these conditions are met, the LSI53C1000 issues a Write and Invalidate command instead of a Memory Write command during all PCI write cycles. Multiple Cache Line Transfers – The Memory Write and Invalidate command can write multiple cache lines of data in a single bus ownership.
Page 38: Pci Cache Mode
Latency – In accordance with the PCI speciﬁcation, the latency timer is ignored when issuing a Memory Write and Invalidate command. Therefore, when a latency time-out occurs, the LSI53C1000 continues to transfer up to a cache line boundary. At that point, the chip relinquishes the bus, and ﬁnishes the transfer at a later time using another bus...
Page 39: Pci Cache Mode Alignment
Memory Read Line (MRL), Memory Read Multiple (MRM), and Memory Write and Invalidate (MWI) are individually software enabled or disabled. Table 2.2 provides information on the PCI cache mode alignment. Table 2.2 PCI Cache Mode Alignment Host Memory 0x00 0x04 0x08 0x0C 0x10...
Page 40 2.1.3.1 Enabling Cache Mode To enable the cache logic to issue PCI cache commands (Memory Read Line, Memory Read Multiple, and Memory Write and Invalidate) on any PCI master operation, the following conditions must be met: • The Cache Line Size Enable bit in the DMA Control (DCNTL) register must be set.
Page 41 If the corresponding cache command is not enabled, the cache logic falls back to the next command enabled. For example, if the Memory Read Multiple command is not enabled and the Memory Read Line command is, Memory Read Line command is issued in place of Memory Read Multiple command.
Page 42 2.1.3.5 Examples The examples in this section employ the following abbreviations: MR = Memory Read, MRL = Memory Read Line, MRM = Memory Read Multiple, MW = Memory Write, MWI = Memory Write and Invalidate. Read Example 1 – Burst = 4 Dwords, Cache Line Size = 4 Dwords: A to B: MRL (6 bytes) A to C:...
Page 43 Read Example 2 – Burst = 8 Dwords, Cache Line Size = 4 Dwords: A to B: MRL (6 bytes) A to C: MRL (13 bytes) A to D: MRM (17 bytes) C to D: MRM (5 bytes) C to E: MRM (21 bytes) D to F: MRM (32 bytes)
Page 44 Write Example 1 – Burst = 4 Dwords, Cache Line Size = 4 Dwords: A to B: MW (6 bytes) A to C: MW (13 bytes) A to D: MW (17 bytes) C to D: MW (5 bytes) C to E: MW (3 bytes) MWI (16 bytes) MW (2 bytes)
Page 45 Write Example 2 – Burst = 8 Dwords, Cache Line Size = 4 Dwords: A to B: MW (6 bytes) A to C: MW (13 bytes) A to D: MW (17 bytes) C to D: MW (5 bytes) C to E: MW (3 bytes) MWI (16 bytes) MW (2 bytes)
Page 46: Scsi Functional Description
2-2 illustrates the relationship between the LSI53C1000 modules. The LSI53C1000 offers low level register access or a high level control interface. Like ﬁrst generation SCSI devices, the LSI53C1000 is accessed as a register-oriented device. The ability to sample and/or assert any signal on the SCSI bus is used in error recovery and diagnostic procedures.
Page 47: Scripts Processor
Chapter 4, “Registers.” 2.2.2 Internal SCRIPTS RAM The LSI53C1000 has 8 Kbytes (2048 x 32 bits) of internal, general purpose RAM. The RAM is designed for SCRIPTS program storage, but is not limited to this type of information. When the chip fetches SCRIPTS...
Page 48: 64-Bit Addressing In Scripts
Chapter 5, “SCSI SCRIPTS Instruction Set.” 2.2.3 64-Bit Addressing in SCRIPTS The PCI interface for the LSI53C1000 provides 64-bit address and data capability in the initiator mode. The chip can also respond to 64-bit addressing in the target mode. 2-20...
Page 49: Hardware Control Of Scsi Activity Led
Interrupt Status Zero (ISTAT0) is set anytime the LSI53C1000 is connected to the SCSI bus either as an initiator or a target. This happens after the LSI53C1000 has successfully completed a selection or when it has successfully responded to a selection or reselection.
Page 50: Designing An Ultra160 Scsi System
2.2.5 Designing an Ultra160 SCSI System Software modiﬁcations are needed to take advantage of the Ultra160 speed in the LSI53C1000. Since Ultra160 SCSI is based on existing SCSI standards, it can use existing drivers if they are able to negotiate for Ultra160 synchronous transfer rates.
Page 51: New Phases On Scsi Bus
CRC – CRC is the error detecting code used in Ultra160 SCSI. Four bytes are transferred with data to increase the reliability of data transfers. CRC is used in the DT Data-In and DT Data-Out phases only. Because CRC is implied with DT mode and only works with DT mode, the DT setting can be used for CRC.
Page 52 2.2.5.2 Parallel Protocol Request CRC, Sync/Wide, DT, Quick Arbitration and Selection (QAS), and “information units” are negotiated with a new SCSI extended message: Byte 0 0x01 Extended message Byte 1 0x06 Length Byte 2 0x04 Parallel Protocol Request (PPR) Byte 3 0xXX Transfer Period Factor Byte 4...
Page 53 Note: For DT mode or when the Protocol Options ﬁeld is nonzero, the Transfer Width Exponent must be one indicating a SCSI width of 16 bits. Note: The Table Indirect data (used during selection/reselection) must be updated to enable certain control bits in the SCNTL4 register.
Page 54 (AIPCNTL0) register indicates if the error is an AIP error. 2.2.5.4 Register Considerations The following is a summary of the registers and bits required to enable Ultra160 SCSI on the LSI53C1000. • The PCI Device ID register value must be 0x21.
Page 55 – Bits [6:4], SCF[2:0] (Synchronous Clock Conversion Factor), select the divisor of the SCLK frequency. The SCLK is divided before its presentation to the synchronous SCSI control logic. – Bit 3, EWS (Enable Wide SCSI), is set to enable wide SCSI. Ultra160 requires wide SCSI.
Page 56 – Bit 6, AIPCKEN (AIP Checking Enable), is set to enable checking of the upper byte lane of protection information during Command, Status, and Message Phases. – Bits [5:4] are reserved. – Bit 3, XCLKH_DT (Extra Clock of Data Hold on DT Transfer Edge) is set to add a clock of data hold to synchronous DT SCSI transfers on the DT edge.
Page 57 – Bit 6, DCRCPC (Disable CRC Protocol Checking) causes the LSI53C1000 to not check for a CRC request prior to a phase change on the SCSI bus. This condition creates a SCSI error condition and makes the device noncompliant with the SPI-3 speciﬁcation.
Page 58 CRCDSEL bits. 2.2.5.5 Using the SCSI Clock Quadrupler The LSI53C1000 can quadruple the frequency of a 40 MHz SCSI clock, allowing the system to perform Ultra160 SCSI transfers. This option is user-selectable with bit settings in the...
Page 59: Prefetching Scripts Instructions
2). 6. Clear the Halt SCSI Clock bit. 2.2.6 Prefetching SCRIPTS Instructions The prefetch logic in the LSI53C1000 fetches 8 Dwords of instructions when enabled by setting the Prefetch Enable bit (bit 5) in the Control (DCNTL) register. The maximum burst size that can be...
Page 60: Opcode Fetch Burst Capability
Setting the Burst Opcode Fetch Enable bit (bit 1) in the DMA Mode (DMODE) register (0x38) causes the LSI53C1000 to burst in the ﬁrst two Dwords of all instruction fetches. If the instruction is a Memory-to- Memory Move, the third Dword is accessed in a separate ownership. If the instruction is an indirect type, the additional Dword is accessed in a subsequent bus ownership.
Page 61: Jtag Boundary Scan Testing
TRST is not implemented. Reset of the JTAG logic through the TAP controller occurs when TMS is held high for at least 5 TCK clock cycles. The LSI53C1000 uses an 8-bit instruction register to support all boundary scan instructions. The data registers included in the device are the Boundary Data register, the IDCODE register, and the Bypass register.
Page 62: Bits Used For Parity/Crc/Aip Control And Generation
This bit enables parity checking during PCI master data Enable (CTEST4), Bit 3 phases. Master Data Parity DMA Status This bit is set when the LSI53C1000, as a PCI master, Error (DSTAT), Bit 6 detects a target device signaling a parity error during a data phase. 2-34...
Page 63: Scsi Parity Errors And Interrupts
CRC request prior to a phase change on the SCSI bus. This condition normally causes a SCSI error condition. Note: Setting this bit makes the LSI53C1000 noncompliant to the SPI-3 speciﬁcation. Do not set this bit under normal operating conditions.
Page 64: Dma Fifo
Byte Lane 7 Byte Lane 6 Byte Lane 5 Byte Lane 4 Byte Lane 3 Byte Lane 2 Byte Lane 1 Byte Lane 0 The LSI53C1000 supports 64-bit memory and automatically supports misaligned DMA transfers. The FIFO allows the LSI53C1000 to support 4, 8, 16, 32, 64, or 128 Dword bursts across the PCI bus interface.
Page 65: Scsi Data Paths
2.2.12 SCSI Data Paths The data path through the LSI53C1000 is dependent on whether data is moved into or out of the chip and whether the SCSI data transfer is asynchronous or synchronous. Figure 2.3 illustrates how data is moved to and from the SCSI bus in each of the different modes.
Page 66 operation with an odd byte count. To recover from all other error conditions, clear the DMA FIFO by setting bit 2 (CLF) in Chip Test Three (CTEST3) and retry the I/O. If the Wide SCSI Send (WSS) bit in the SCSI Control Two (SCNTL2) register is set when a phase mismatch occurs, then adjustments must be made to the previous block move, not the current block move loaded into...
Page 67: Scsi Bus Interface
The LSI53C1000 performs SE and LVD transfers. 2.2.13.1 SCSI Bus Modes To increase device connectivity and SCSI cable length, the LSI53C1000 features LVDlink technology, the LSI Logic implementation of LVD SCSI. LVDlink transceivers provide the inherent reliability of differential SCSI and a long-term migration path for faster SCSI transfer rates.
Page 68: Select/Reselect During Selection/Reselection
For information on terminators that support LVD, refer to the SPI-3 draft standard. Note: If the LSI53C1000 is used in a design with an 8-bit SCSI bus, all 16 data lines must be terminated. Figure 2.4 Regulated Termination for Ultra160 SCSI −...
Page 69: Synchronous Operation
ID (SCID) bits 5 and 6, respectively) should both be asserted, enabling the LSI53C1000 to respond as an initiator or as a target. If only selection is enabled, the LSI53C1000 cannot be reselected as an initiator. Status bits, in the...
Page 70: Scf Divisor Values
This bit only impacts DT transfers as it only affects data hold to the DT edge. Setting this bit reduces the synchronous transfer send rate but does not reduce the rate at which the LSI53C1000 receives outbound REQs, ACKs, or data.
Page 71 This bit impacts DT and ST transfers as it affects data hold to the ST edge. Setting this bit reduces the synchronous transfer send rate but does not reduce the rate at which the LSI53C1000 receives outbound REQs, ACKs, or data.
Page 72 To conﬁgure the LSI53C1000 for Ultra160 DT transfers, perform the following steps: Step 1. Enable the SCSI Clock Quadrupler – The LSI53C1000 can quadruple the frequency of a 40 MHz SCSI clock, allowing the system to perform Ultra160 SCSI transfers. This option is...
Page 73: Interrupt Handling
However, certain interrupt situations must be handled by the external microprocessor. This section explains all aspects of interrupts as they apply to the LSI53C1000. 2.2.16.1 Polling and Hardware Interrupts The external microprocessor is informed of an interrupt condition by polling or hardware interrupts.
Page 74 A hybrid approach uses hardware interrupts for long waits and polling for short waits. The SCSI interrupt is routed to PCI Interrupt INTA/. 2.2.16.2 Registers The registers in the LSI53C1000 used for detecting or deﬁning interrupts Interrupt Status Zero (ISTAT0), Interrupt Status One (ISTAT1), SCSI...
Page 75 CRC Control One (CRCCNTL1) register. If the LSI53C1000 is sending data to the SCSI bus and a fatal SCSI interrupt condition occurs, data could remain in the DMA FIFO. To determine if the DMA FIFO is empty, check the DMA FIFO Empty (DFE)
Page 76 DSTAT, and clears the DIP bit in Interrupt Status Zero (ISTAT0). Since the LSI53C1000 stacks interrupts, reading DSTAT does not necessarily clear the register as additional interrupts may be pending. Bit 7 (DFE) in the DMA Status (DSTAT) register, is purely a status bit;...
Page 77 CPU. This prevents an interrupt when arbitration is complete (CMP set), when the LSI53C1000 is selected or reselected (SEL or RSL set), when the initiator asserts ATN (target mode: SATN/ active), or when the General Purpose or Handshake-to-Handshake timers expire.
Page 78 Interrupt Status Zero (ISTAT0) inform the system of interrupts, not the INTA/ pin. 2.2.16.5 Stacked Interrupts The LSI53C1000 stacks interrupts, if they occur, one after the other. If the SIP or DIP bits in the Interrupt Status Zero (ISTAT0) register are set (ﬁrst level), then there is already at least one pending interrupt.
Page 79 These ‘locked out’ SCSI interrupts are posted as soon as the DMA FIFO is empty. 2.2.16.6 Halting in an Orderly Fashion When an interrupt occurs, the LSI53C1000 attempts to halt in an orderly fashion. • If the interrupt occurs in the middle of an instruction fetch, the fetch is completed, except in the case of a Bus Fault.
Page 80 2.2.16.7 Sample Interrupt Service Routine The following is a sample of an interrupt service routine for the LSI53C1000. It can be repeated if polling is used, or should be called when the INTA/ pin is asserted if hardware interrupts are used.
Page 81: Interrupt Routing
2.2.17 Interrupt Routing This section documents the recommended approach to RAID ready interrupt routing for the LSI53C1000. In order to be compatible with RAID upgrade products and the LSI53C1000, the following requirements must be met: • When a RAID upgrade card is installed in the upgrade slot, interrupts...
Page 82: Interrupt Routing Hardware Using The Lsi53C1000
The ﬁrst option is to have the SCSI core load its PCI Subsystem ID using a serial EPROM on power-up. If bit 15 in this ID is set, the LSI Logic BIOS and operating system drivers will ignore the chip. This makes it possible to control the assignment of the mainboard SCSI cores using a conﬁguration utility.
Page 83: Chained Block Moves
BIOS calls when searching for PCI devices. 2.2.18 Chained Block Moves Since the LSI53C1000 has the capability to transfer 16-bit wide SCSI data, a unique situation occurs when dealing with odd bytes. The Chained Move (CHMOV) SCRIPTS instruction along with the Wide SCSI...
Page 84 transfers, in the chain byte holding register for synchronous transfers). The stored byte is combined with the ﬁrst byte of the following CHMOV instruction. CHMOV 0x5, 0x9 when Data-In Moves ﬁve bytes from address 0x09 in the host memory to the SCSI bus. The data in address 0x09 is married with the stored data (0x07) and transferred to the SCSI bus.
Page 85 instruction. Under this condition the high-order byte is not transferred out the DMA channel to memory. Instead, it is stored in the SCSI Wide Residue (SWIDE) register and the WSR ﬂag is set. The hardware uses the WSR bit to determine what behavior must occur at the start of the next data receive transfer.
Page 86 For receive data (Data-In for the initiator or Data-Out for the target), a Chained Block Move instruction indicates that if a partial transfer occurred at the end of the instruction the WSR ﬂag is set. The high-order byte of the last SCSI transfer is stored in the SCSI Wide Residue (SWIDE) register rather than transferred to memory.
Page 87: Parallel Rom Interface
2.3 Parallel ROM Interface The LSI53C1000 supports up to 1 Mbyte of external memory in binary increments from 16 Kbytes to allow the use of expansion ROM for add-in PCI cards. This interface is designed for low-speed operations such as downloading instruction code from ROM; it is not intended for dynamic activities such as executing instructions.
Page 88: Parallel Rom Support
MAD[2]. If the external memory interface is not used, MAD[3:1] should be pulled HIGH. The LSI53C1000 allows the system to determine the size of the available external memory using the Expansion ROM Base Address register in the PCI conﬁguration space. For more information on how this works, refer to the PCI speciﬁcation or the Expansion ROM Base Address register...
Page 89: Serial Eeprom Interface
2.4 Serial EEPROM Interface The LSI53C1000 implements an interface permitting attachment of a serial EEPROM device to the GPIO[0] and GPIO[1] pins. There are two modes of operation relating to the serial EEPROM, the Subsystem ID register, and the Subsystem Vendor ID register. These modes are programmable through the MAD[7] pin, which is sampled at power-up.
Page 90: No Download Mode
PCI speciﬁcation, with a default value of 0x1000 and 0x1000 respectively. 2.5 Power Management The LSI53C1000 complies with the PCI Bus Power Management Interface Speciﬁcation, Revision 1.1, in which the D0, D1, D2, and D3 are deﬁned.
Page 91: Power State D0
Power state D1 is a lower power state than D0. In this state the LSI53C1000 core is in the snooze mode and the SCSI clock is disabled. In the snooze mode, a SCSI reset does not generate an INT/ signal.
Page 92: Power State D2
D3, which clears all pending interrupts and 3-states the SCSI bus. In addition, the PCI Command register is cleared. If the LSI53C1000 is placed in power state D3, the Clock Quadrupler is disabled, which results in additional power savings. 2-64...
Page 93: Chapter 3 Signal Descriptions
Chapter 3 Signal Descriptions This chapter describes the input and output signals of the LSI53C1000. The chapter consists of the following sections: • Section 3.1, “Signal Organization” • Section 3.2, “Internal Pull-ups and Pull-downs on LSI53C1000 Signals” • Section 3.3, “PCI Bus Interface Signals”...
Page 94 The PCI Interface contains several functional groups of signals. The SCSI Bus Interface contains one functional group of signals, as illustrated in Figure 3.1. There are ﬁve signal type deﬁnitions: Input, a standard input-only signal. Output, a standard output driver (typically a Totem Pole output). Input and output (bidirectional).
Page 95: Lsi53C1000 Signal Grouping
Figure 3.1 LSI53C1000 Signal Grouping LSI53C1000 SCLK ENABLE66 System M66EN RST/ SD[15:0]/ SDP[1:0]/ AD[63:0] Address DIFFSENS C_BE[7:0]/ SCSI Data PAR64 SC_D/ Interface SI_O/ ACK64/ SMSG/ REQ64/ SREQ/ FRAME/ SACK/ Interface TRDY/ SBSY/ Control IRDY/ SATN/ STOP/ SRST/ Interface DEVSEL/ SSEL/...
Page 96: Internal Pull-Ups And Pull-Downs On Lsi53C1000 Signals
3.2 Internal Pull-ups and Pull-downs on LSI53C1000 Signals Several LSI53C1000 signals use internal pull-ups or pull-downs. Table 3.1 describes the conditions that enable these pull-ups and pull-downs. Table 3.1 LSI53C1000 Internal Pull-ups and Pull-downs Pull-up Pin Name Current Conditions for Pull-up 25 µA...
Page 97: System Signals
3.3.1 System Signals Table 3.2 describes the signals for the System Signals group. Table 3.2 System Signals Name Bump Type Strength Description Clock provides timing for all transactions on the PCI bus and is an input to every PCI device. All other PCI signals are sampled on the rising edge of CLK and other timing parameters are deﬁned with respect to this edge.
Page 98: Address And Data Signals
3.3.2 Address and Data Signals Table 3.3 describes the Address and Data Signals group. Table 3.3 Address and Data Signals Name Bump Type Strength Description AD[63:0] Y5, AB5, AC5, AA6, 8 mA PCI Physical longword Address and Data are Y6, AB6, AC6, AA7, multiplexed on the same PCI pins.
Page 99: Interface Control Signals
3.3.3 Interface Control Signals Table 3.4 describes the Interface Control Signals group. Table 3.4 Interface Control Signals Name Bump Type Strength Description ACK64/ S/T/S 8 mA PCI Acknowledge 64-bit transfer is driven by the current bus target to indicate its ability to transfer 64-bit data. REQ64/ S/T/S 8 mA PCI Request 64-bit transfer is driven by the current bus master to indicate a request to transfer 64-bit data.
Page 100: Arbitration Signals
3.3.4 Arbitration Signals Table 3.5 describes the Arbitration Signals group. Table 3.5 Arbitration Signals Name Bump Type Strength Description REQ/ 8 mA PCI Request indicates to the system arbiter that this agent requests use of the PCI bus. This is a point-to-point signal. Every master has its own REQ/ signal.
Page 101: Interrupt Signals
3.3.6 Interrupt Signals Table 3.7 describes the Interrupt Signals group. Table 3.7 Interrupt Signals Name Bump Type Strength Description INTA/ 8 mA PCI Interrupt. This signal, when asserted LOW, indicates that an interrupt condition requires service from the host CPU. The output drive of this pin is an open drain.
Page 102: Scsi Signals
The following tables describe the SCSI signals. Table 3.9 describes the SCSI Signals and Table 3.10 describes the SCSI Control Signals. Table 3.9 SCSI Signals Name Bump Type Strength Description SD[15:0]− B5, C5, B4, C4, SCSI Data. D19, A19, D18, 48 mA A18, D11, A9, D9, SCSI...
Page 103 Table 3.9 SCSI Signals (Cont.) Name Bump Type Strength Description DIFFSENS SCSI Differential Sense pin detects the present mode of the SCSI bus when connected to the DIFFSENS signal on the physical SCSI bus. LVD Mode: If a voltage between 0.7 V and 1.9 V is present, the SCSI bus operates in the LVD mode.
Page 104: Scsi Control Signals
Table 3.10 SCSI Control Signals Name Bump Type Strength Description SCSI Control includes the following signals: SC_D− SCSI phase line, command/data. 48 mA SC_D+ SCSI SI_O− SCSI phase line, input/output. SI_O+ LVD: 12 mA SMSG− UniLVD SCSI phase line, message. SMSG+ SREQ−...
Page 105: General Purpose I/O (Gpio) Signals
MAD7 pin, to serve as the clock signal for the serial EEPROM interface. If bit 7 of the General Purpose Pin Control (GPCNTL) register is set, this pin drives LOW when the LSI53C1000 is the bus master. GPIO2 AA16 8 mA General Purpose I/O pin 2.
Page 106: Flash Rom And Memory Interface Signals
Memory Output Enable. This pin is an output TESTOUT enable signal to an external EPROM or ﬂash memory during read operations. It is also used to test the connectivity of the LSI53C1000 signals in the “AND-tree” test mode. MAS0/ AC18 4 mA Memory Address Strobe 0.
Page 107: Test Interface Signals
Bump Type Strength Description Internal Test Signals: SCAN_MODE Scan Mode. For LSI Logic test purposes only. This pin has a static pull-down. TEST_HSC Test Halt SCSI Clock. For LSI Logic test purposes only. Pulled LOW internally. This signal can also cause a full chip reset.
Page 108: Power And Ground Signals
3.8 Power and Ground Signals Table 3.14 describes the Power and Ground Signal group. Table 3.14 Power and Ground Signals Name Bump Type Strength Description C3, C21, D4, D12, D20, Ground for PCI bus SS_IO K10–14, L10–14, M4, M10–14, drivers/receivers, SCSI bus M20, N10–14, P10–14, Y4, drivers/receivers, local memory Y12, Y20, AA3, AA21...
Page 109: Mad Bus Programming
Table 3.14 Power and Ground Signals (Cont.) Name Bump Type Strength Description A1, A13, A23, AA14, AA15, These pins are reserved or have AA23, AB15, AB22, AC15, no internal connection. AC16, B13, B16, B21, D16, D22, D23, E20, E21, E22, E23, F2, F20, F21, F22, F23, G3, G21, G22, G23, H20, H21, H22, H23, J20, J21, J22, J23,...
Page 110: Mad[3:1] Pin Decoding
• MAD[6] – Reserved. • MAD[5] – Reserved. • MAD[4] – Reserved. • MAD[3:1] – These pins set the size of the external expansion ROM device attached. Table 3.15 provides the encoding for these pins. A “0” indicates a pull-down resistor is attached while a “1” indicates a pull-up resistor attached.
Page 111: Chapter 4 Registers
PCI-compliant registers is optional. In the LSI53C1000, registers that are not supported are not writable and return all zeros when read. Only those registers and bits that are currently supported by the LSI53C1000 are described in this chapter. Do not access bits marked as Reserved.
Page 112: Pci Conﬁguration Register Map
Table 4.1 PCI Conﬁguration Register Map 16 15 0 Address Page Device ID Vendor ID 0x00 Status Command 0x04 Class Code (CC) Revision ID (RID) 0x08 Reserved Header Type (HT) Latency Timer (LT) Cache Line Size (CLS) 0x0C Base Address Register Zero (BAR0) (I/O) 0x10 Base Address Register One (BAR1) (MEMORY) bits [31:0]...
Page 113 The SCSI Command register provides coarse control over a device’s ability to generate and respond to PCI cycles. When a zero is written to this register, the LSI53C1000 is logically disconnected from the PCI bus for all accesses except conﬁguration accesses.
Page 114 Reserved Enable Bus Mastering This bit controls the ability of the LSI53C1000 to act as a master on the PCI bus. A value of zero disables this device from generating PCI bus master accesses. A value of one allows the LSI53C1000 to behave as a bus master.
Page 115 15 and not affect any other bits, write the value 0x8000 to the register. Detected Parity Error (from Slave) This bit is set by the LSI53C1000 upon the detection of a data parity error, even if data parity error handling is disabled.
Page 116 Fast Back to Back Capable This bit is zero. Reserved 66 MHz Capable When set, this bit indicates that the LSI53C1000 is capable of 66 MHz PCI operation. This bit is controlled by the ENABLE66 pin, which has a static pull-up. New Capabilities This bit is set to indicate a list of extended capabilities such as PCI Power Management.
Page 117 Registers: 0x09–0x0B Class Code (CC) Read Only Class Code [23:0] This 24-bit register identiﬁes the generic function of the device. The upper byte of this register is a base class code, the middle byte is a subclass code, and the lower byte identiﬁes a speciﬁc register-level programming interface.
Page 118 This 8-bit register identiﬁes the layout of bytes 0x10 through 0x3F in conﬁguration space and also whether or not the device contains multiple functions. Since the LSI53C1000 is not a multifunction controller, the value of this register is 0x00. Registers...
Page 119 [31:0] This base address register is used to map the operating register set into I/O space. The LSI53C1000 requires 256 bytes of I/O space for this base address register. Bit 0 is hardwired to one. Bit 1 is reserved and returns a zero on all reads.
Page 120 32 bits of the memory address. The default value of this register is 0x00000000. The LSI53C1000 requires 1024 bytes of memory space. For detailed information on the operation of this register, refer to the PCI 2.2 speciﬁcation.
Page 121 Bits [12:0] are hardwired to 0b0000000000100. The default value of this register is 0x00000004. The LSI53C1000 requires 8192 bytes of memory space for SCRIPTS RAM. For detailed information on the operation of this register, refer to the PCI 2.2 speciﬁcation.
Page 122 Registers: 0x24–0x27 Reserved This register is reserved. Registers: 0x28–0x2B Reserved This register is reserved. Registers: 0x2C–0x2D Subsystem Vendor ID (SVID) Read Only SVID If MAD7 is HIGH If MAD7 is LOW SVID Subsystem Vendor ID [15:0] This 16-bit register is used to uniquely identify the vendor manufacturing the add-in board or subsystem where this PCI device resides.
Page 123 If the external serial EEPROM interface is enabled (MAD[7] LOW), this register is automatically loaded at power-up from the external serial EEPROM and contains the value downloaded from the serial EEPROM or, if the download fails, a value of 0x0000. If the external serial EEPROM interface is disabled (MAD[7] HIGH), this register returns a value of 0x1000.
Page 124 Expansion ROM Base Address (ERBA) register with all ones and then reading back the register. The LSI53C1000 responds with zeros in all don’t care locations. The least signiﬁcant one (1) that remains represents the binary version of the external memory size.
Page 125 Register: 0x34 Capabilities Pointer (CP) Read Only Capabilities Pointer [7:0] This register indicates that the ﬁrst extended capability register is located at offset 0x40 in PCI Conﬁguration Space. Registers: 0x35–0x37 Reserved This register is reserved. Registers: 0x38–0x3B Reserved This register is reserved. PCI Conﬁguration Registers 4-15...
Page 126 Register: 0x3C Interrupt Line (IL) Read/Write Interrupt Line [7:0] This register is used to communicate interrupt line routing information. POST software writes the routing information into this register as it conﬁgures the system. The value in this register tells which input of the system interrupt controller(s) the device’s interrupt pin is connected to.
Page 127 This register is used to specify the desired settings for latency timer values. Min_Gnt is used to specify how long a burst period the device needs. The value speciﬁed in these registers is in units of 0.25 µs. The LSI53C1000 sets this register to 0x11. Register: 0x3F...
Page 128 AUX_C PMEC VER[2:0] PMES PME_Support [15:11] Bits [15:11] deﬁne the power management states in which the LSI53C1000 will assert the PME pin. These bits are all set to zero because the LSI53C1000 does not provide a PME signal. 4-18 Registers...
Page 129 D2_Support The LSI53C1000 sets this bit to indicate support for power management state D2. Bits 9 and 10 are set to one indicating support for the D1 and D2 power states. D1_Support The LSI53C1000 sets this bit to indicate support for power management state D1.
Page 130 DSLT Data_Select [12:9] The LSI53C1000 does not support the Data register. Therefore, these four bits are always cleared. PME_Enable The LSI53C1000 always returns zero for this bit to indicate that PME assertion is disabled. Reserved [7:2] PWS[1:0] Power State [1:0] Bits [1:0] are used to determine the current power state of the LSI53C1000.
Page 131: Scsi Registers
Load and Store SCRIPTS instructions, Memory-to-Memory Moves, Read/Write SCRIPTS instructions, or the CPU with SCRIPTS not running. Note: The only registers that the host CPU can access while the LSI53C1000 is executing SCRIPTS are the Interrupt Status Zero (ISTAT0), Interrupt Status One...
Page 132: Scsi Register Map
Table 4.2 SCSI Register Map Address Page SCNTL3 SCNTL2 SCNTL1 SCNTL0 0x00 4-23 GPREG SDID SXFER SCID 0x04 4-32 SBCL SSID SOCL SFBR 0x08 4-36 SSTAT2 SSTAT1 SSTAT0 DSTAT 0x0C 4-39 0x10 4-45 MBOX1 MBOX0 ISTAT1 ISTAT0 0x14 4-46 CTEST3 CTEST2 CTEST1 CTEST0...
Page 133 Simple arbitration Reserved Reserved Full arbitration, selection/reselection Simple Arbitration The LSI53C1000 waits for a bus free condition to occur. It asserts SBSY/ and its SCSI ID, contained in the SCSI Chip ID (SCID) register, onto the SCSI bus. If the SSEL/ signal is asserted by another SCSI...
Page 134 2. START Start Sequence When this bit is set, the LSI53C1000 starts the arbitration sequence indicated by the Arbitration Mode bits. The Start Sequence bit is accessed directly in low-level mode; during SCSI SCRIPTS operations, this bit is controlled by the SCRIPTS processor.
Page 135 WATN Select with SATN/ on a Start Sequence When this bit is set and the LSI53C1000 is in the initiator mode, the SATN/ signal is asserted during selection of a SCSI target device. This is to inform the target that the LSI53C1000 has a message to send.
Page 136 SACK/ during the byte transfer with the parity error. Also set the Enable Parity/CRC/AIP Checking bit for the LSI53C1000 to assert SATN/ in this manner. A parity error or CRC error is detected on data received from the SCSI bus.
Page 137 If the LSI53C1000 is receiving data, any data residing in the DMA FIFO is sent to memory before halting. When this bit is set, the LSI53C1000 does not halt the SCSI transfer when SATN/ or a Parity/CRC/AIP error is received.
Page 138 Connected This bit is automatically set any time the LSI53C1000 is connected to the SCSI bus as an initiator or as a target. It is set after the LSI53C1000 successfully completes arbitration or when it has responded to a bus-initiated selection or reselection.
Page 139: Scsi Shadow Registers
• The abort completes because the LSI53C1000 loses arbitration. This is detected by the clearing of the Immediate Arbitration bit. Do not use the Lost...
Page 140 should be cleared with a register write (Move 0x00 To SCSI Control Two (SCNTL2)) before the SCSI core expects a disconnect to occur, normally prior to sending an Abort, Abort Tag, Bus Device Reset, Clear Queue or Release Recovery message, or before deasserting SACK/ after receiving a Disconnect command or Command Complete message.
Page 141 Wide SCSI Receive When read, this bit returns the value of the Wide SCSI Receive (WSR) ﬂag. Setting this bit clears the WSR ﬂag. This bit is self-clearing. For more information refer to Section 2.2.18, “Chained Block Moves.” Register: 0x03 SCSI Control Three (SCNTL3) Read/Write SCF[2:0]...
Page 142 Enable Response to Selection When this bit is set, the LSI53C1000 is able to respond to bus-initiated selection at the chip ID in the Response ID Zero (RESPID0) Response ID One (RESPID1) registers.
Page 143 SCSI bus. The IDs that the LSI53C1000 responds to when selected or reselected are conﬁgured in the Response ID Zero (RESPID0) Response ID One (RESPID1) registers. The priority of the 16 possible IDs, in descending order is:...
Page 144: Maximum Synchronous Offset
A value of 0 in these bits program the device to perform asynchronous transfers. A value of 1 during DT transfers is illegal and will result in data corruption. Table 4.3 Maximum Synchronous Offset Synchronous Offset 0-Asynchronous Reserved Reserved Register: 0x06 SCSI Destination ID (SDID) Read/Write Reserved...
Page 145 EEPROM. GPIO1 is used as a clock, with the GPIO0 pin serving as data. LSI Logic software also reserves the use of GPIO[4:2]. If there is a need to use GPIO[4:2], please check with LSI Logic for additional information.
Page 146 [7:0] This register contains the ﬁrst byte received in any asynchronous information transfer phase. For example, when a LSI53C1000 is operating in the initiator mode, this register contains the ﬁrst byte received in the Message-In, Status, and Data-In phases. When a Block Move instruction is executed for a particular phase, the ﬁrst byte received is stored in this...
Page 147: Scsi Scripts
I/O. Some bits are set or cleared when executing SCSI SCRIPTS. Do not write to the register once the LSI53C1000 starts executing normal SCSI SCRIPTS. Assert SCSI REQ/ Signal Assert SCSI ACK/ Signal...
Page 148 Encoded Destination SCSI ID [3:0] Reading the SSID register immediately after the LSI53C1000 is selected or reselected returns the binary-encoded SCSI ID of the device that performed the operation. These bits are invalid for targets that are selected under the single initiator option of the SCSI-1 speciﬁcation.
Page 149 Reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register in case additional interrupts are pending (the LSI53C1000 stacks interrupts). The DIP bit in Interrupt Status Zero (ISTAT0) register is also cleared.
Page 150 MDPE Master Data Parity Error This bit is set when the LSI53C1000, acting as a PCI master, detects a data parity error, or, when acting as a target device, signals a parity error during a data phase. This bit is completely disabled by the Master Parity Error...
Page 151 Data (bit 18) and Compare Phase (bit 17) bits are set in the DMA Byte Counter (DBC) register while the LSI53C1000 is in target mode. • During a Transfer Control instruction, the Carry Test bit (bit 21) is set and either the Compare Data (bit 18) or Compare Phase (bit 17) bit is set.
Page 152 ARBIP Arbitration in Progress Arbitration in Progress (ARBIP = 1) indicates that the LSI53C1000 has detected a Bus Free condition, asserted SBSY, and asserted its SCSI ID onto the SCSI bus. Lost Arbitration When set, LOA indicates that the LSI53C1000 has...
Page 153 Won Arbitration When set, WOA indicates that the LSI53C1000 has detected a Bus Free condition, arbitrated for the SCSI bus and won arbitration. The arbitration mode selected in SCSI Control Zero (SCNTL0) register must be full arbitration and selection to set this bit.
Page 154 SCSI C_D/ Signal This SCSI phase status bit is latched on the asserting edge of SREQ/ when operating in either the initiator or target mode. This bit is set when the corresponding signal is active. This bit is useful when operating in the low-level mode.
Page 155 (SCNTL1). It allows the user to detect the case in which a target device disconnects, and then a SCSI device selects or reselects the LSI53C1000. If the Connected bit and the LDSC bit are asserted, a disconnect is indicated. This bit is set when the Connected bit in SCNTL1 is off.
Page 156 ABRT Abort Operation Setting this bit aborts the current operation under execution by the LSI53C1000. If this bit is set and an interrupt is received, clear this bit before reading the Status (DSTAT) register to prevent further aborted interrupts from being generated.
Page 157 The SCRIPTS processor may set this bit using a SCRIPTS register write instruction. An external processor may also set it while the LSI53C1000 is executing a SCRIPTS operation. This bit enables the LSI53C1000 to notify an external processor of a predeﬁned condition while SCRIPTS are running.
Page 158 After it has been set, this bit must be written to one to clear SCSI Interrupt Pending This status bit is set when an interrupt condition is detected in the SCSI portion of the LSI53C1000. The following conditions cause a SCSI interrupt to occur: •...
Page 159 SCRIPTS engine is not active. This bit is read only. Writes do not affect the value of this bit. SYNC_IRQD Setting this bit disables the INTA/ pin for the LSI53C1000, except for the SCSI gross error, bus fault, residual data in SCSI FIFO, and data underﬂow interrupts. Clearing this bit enables normal operation of the INTA/ pin.
Page 160 remains asserted until the interrupt is serviced. At this point the interrupt line is blocked for future interrupts until this bit is cleared. In addition, this bit may be read and written while SCRIPTS are executing. Register: 0x16 Mailbox Zero (MBOX0) Read/Write MBOX0 MBOX0...
Page 161 Register: 0x18 Chip Test Zero (CTEST0) Read/Write Byte Empty in DMA FIFO [7:0] These bits identify the lower bytes in the DMA FIFO that are empty. Each bit corresponds to a byte lane in the DMA FIFO. For example, if byte lane three is empty, then FMT bit 3 is set.
Page 162 Register: 0x1A Chip Test Two (CTEST2) Read Only (bit 3 write) SIGP PCICIE Reserved SIGP Signal Process This bit is a copy of the SIGP bit in the Interrupt Status Zero (ISTAT0) register (bit 5). The SIGP bit is used to signal a running SCRIPTS instruction.
Page 163 Next Address (DNAD) register. This bit is not self-clearing; clear it once the data is successfully transferred by the LSI53C1000. Note: Polling of FIFO ﬂags is allowed during ﬂush operations. SCSI Registers...
Page 164 Clear DMA FIFO When this bit is set, all data pointers for the DMA FIFO are cleared. Any data in the FIFO is lost. After the LSI53C1000 successfully clears the appropriate FIFO pointers and registers, this bit automatically clears. Note: This bit does not clear the data visible at the bottom of the FIFO.
Page 165 Setting this bit enables parity checking during master data phases. A parity error during a bus master read is detected by the LSI53C1000. A parity error during a bus master write is detected by the target, and the LSI53C1000 is informed of the error by the PERR/ pin being asserted by the target.
Page 166 DMA FIFO FBL3 FBL2 FBL1 FBL0 Byte Lane Pins D[39:32] D[47:40] D[53:48] D[63:54] These bits steer the contents of the Chip Test Six (CTEST6) register to the appropriate byte lane of the 64-bit DMA FIFO. If the FBL3 bit is set, then FBL2 through FBL0 determine which of eight byte lanes can be read or written.
Page 167 Reserved [5:3] Burst Length Bit 2 This bit works with bits 6 and 7 (BL[1:0]) in the Mode (DMODE) register to determine the burst length. For complete deﬁnitions of this ﬁeld, refer to the descriptions of DMODE bits 6 and 7. Reserved [1:0] Register: 0x23...
Page 168 0xFFFFFF. If the instruction is a Block Move and a value of 0x000000 is loaded into the DBC register, an illegal instruction interrupt occurs if the LSI53C1000 is not in the target mode, Command phase. DMA Byte Counter (DBC) register is also used to hold the least signiﬁcant 24 bits of the ﬁrst Dword of a...
Page 169 DCMD DMA Command [7:0] This 8-bit register determines the instruction for the LSI53C1000 to execute. This register has a different format for each instruction. For a complete description Chapter 5, “SCSI SCRIPTS Instruction Set.” Registers: 0x28–0x2B DMA Next Address (DNAD)
Page 170: Second Dword
Registers: 0x2C–0x2F DMA SCRIPTS Pointer (DSP) Read/Write DMA SCRIPTS Pointer [31:0] To execute SCSI SCRIPTS, the address of the ﬁrst SCRIPTS instruction must be written to this register. In normal SCRIPTS operation, once the starting address of the SCRIPT is written to this register, SCRIPTS are automatically fetched and executed until an interrupt condition occurs.
Page 171 This value is also independent of the width (64-bit or 32-bit) of the data transfer on the PCI bus. The LSI53C1000 asserts the Bus Request (PCIREQ/) output when the DMA FIFO can accommodate a transfer of at least one burst threshold of data. Bus Request...
Page 172 The LSI53C1000 inserts a “fairness delay” of four CLKs between burst transfers (set in BL[2:0]) during normal operation. The fairness delay is not inserted during PCI retry cycles. This gives the CPU and other bus master devices the opportunity to access the PCI bus between bursts.
Page 173 Multiple command is used on all read cycles when it is legal. Burst Opcode Fetch Enable Setting this bit causes the LSI53C1000 to fetch instructions in burst mode. Speciﬁcally, the chip bursts in the ﬁrst two Dwords of all instructions using a single bus ownership.
Page 174 Register: 0x39 DMA Interrupt Enable (DIEN) Read/Write MDPE ABRT This register contains the interrupt mask bits corresponding to the interrupting conditions described in the DMA Status (DSTAT) register. An interrupt is masked by clearing the appropriate mask bit. Masking an interrupt prevents INTA/ from being asserted for the corresponding interrupt, but the status bit is still set in the DMA Status (DSTAT)
Page 175 8 Dwords of instructions and instruction operands in bursts of 4 or 8 Dwords. Prefetching instructions allows the LSI53C1000 to make more efﬁcient use of the system PCI bus, thus improving overall system performance. A ﬂush occurs whenever the PFF bit is set, on all transfer...
Page 176 PCI bus. Prefetches of SCRIPTS instructions are 32-bits in width. Single-Step Mode Setting this bit causes the LSI53C1000 to stop after executing each SCRIPTS instruction and to generate a single step interrupt. When this bit is cleared the LSI53C1000 does not stop after each instruction.
Page 177 DMA SCRIPTS Pointer (DSP) register when this bit is set. This bit is required if the LSI53C1000 is in one of the following modes: • Manual start mode – Bit 0 in the DMA Mode...
Page 178 Registers: 0x3C–0x3F Adder Sum Output (ADDER) Read Only ADDER ADDER Adder Sum Output [31:0] This register contains the output of the internal adder, and is used primarily for test purposes. The power-up value for this register is indeterminate. Register: 0x40 SCSI Interrupt Enable Zero (SIEN0) Read/Write This register contains the interrupt mask bits corresponding to the...
Page 179 Selected When set, this bit indicates the LSI53C1000 is selected by a SCSI initiator device. For this to occur, set the Enable Response to Selection bit in the SCSI Chip ID (SCID) register. Reselected When set, this bit indicates the LSI53C1000 is reselected by a SCSI target device.
Page 180 SCSI Reset Condition This bit indicates assertion of the SRST/ signal by the LSI53C1000 or any other SCSI device. This condition is edge-triggered, so multiple interrupts cannot occur because of a single SRST/ pulse.
Page 181 [7:5] SBMC SCSI Bus Mode Change Setting this bit allows the LSI53C1000 to generate an interrupt when the DIFFSENS pin detects a change in voltage level that indicates the SCSI bus has changed between SE, LVD, or HVD modes. For example, when...
Page 182 Reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register because additional interrupts may be pending; the LSI53C1000 stacks interrupts. SCSI interrupt conditions are individually masked through the...
Page 183 Selected This bit is set when the LSI53C1000 is selected by another SCSI device. For the LSI53C1000 to respond to selection attempts, the Enable Response to Selection bit must be set in the SCSI Chip ID (SCID) register. The Response ID Zero (RESPID0)
Page 184 Two (CCNTL2) register. Unexpected Disconnect This bit is set when the LSI53C1000 is operating in the initiator mode and the target device unexpectedly disconnects from the SCSI bus. This bit is only valid when the LSI53C1000 operates in the initiator mode.
Page 185 SE, LVD, or HVD modes. HVD is not supported. Reserved Selection or Reselection Time-Out This bit is set when the SCSI device which the LSI53C1000 is attempting to select or reselect does not respond within the programmed time-out period. See the description of the SCSI Timer Zero (STIME0) register, bits [3:0], for more information on the time-out timer.
Page 186 Register: 0x44 Reserved This register is reserved. Register: 0x45 SCSI Wide Residue (SWIDE) Read/Write SWIDE SWIDE SCSI Wide Residue [7:0] After a wide SCSI data receive operation, this register contains a residual data byte if the last byte received was never sent across the DMA bus.
Page 187 Register: 0x47 General Purpose Pin Control (GPCNTL) Read/Write LEDC GPIO[4:2] GPIO[1:0] This register is used to determine if the pins controlled by the General Purpose (GPREG) register are inputs or outputs. Bits [4:0] in GPCNTL correspond to bits [4:0] in the GPREG register. When the bits are enabled as inputs, an internal pull-up is also enabled.
Page 188 GPIO[1:0] GPIO Enable [1:0] These bits are set at power-up causing the GPIO1 and GPIO0 pins to become inputs. Clearing these bits cause GPIO[1:0] to become outputs. Register: 0x48 SCSI Timer Zero (STIME0) Read/Write HTH[3:0] SEL[3:0] HTH[3:0] Handshake-to-Handshake Timer Period [7:4] These bits select the handshake-to-handshake time-out period, which is the maximum time between SCSI...
Page 189 SEL[3:0] Selection Time-Out [3:0] These bits select the SCSI selection/reselection time-out period. When this timing (plus the 200 µs selection abort time) is exceeded, the STO bit in the SCSI Interrupt Status One (SIST1) register is set. For a more detailed explanation of interrupts, refer to Chapter 2, “Functional Description.”...
Page 190 Minimum Time-out HTHSF = 0, HTHSF = 1, HTH[3:0], SEL[3:0], GEN[3:0] GENSF = 0 GENSF = 1 1011 128 ms 1100 256 ms 4.1 s 1101 512 ms 8.2 s 1110 1.024 s 16.4 s 1111 2.048 s 32.8 s HTHSF Handshake to Handshake Timer Scale Factor Setting this bit causes this timer to shift by a factor of 16.
Page 191 SCSI Selection or Reselection phase. These bits are read only and contain the encoded value of 16 possible IDs that could be used to select the LSI53C1000. During a SCSI Selection or Reselection phase when a valid ID SCSI Registers...
Page 192 LSI53C1000 responds to that ID, the “selected as” ID is written into these bits. These bits are used with Response ID Zero (RESPID0) Response ID One (RESPID1) registers to allow response to multiple IDs on the bus.
Page 193 IRM[1:0] Interrupt Routing Mode [1:0] The LSI53C1000 supports four different interrupt routing modes. These modes are described in the following table. Mode 0, the default mode, is compatible with RAID upgrade products. SCSI Registers...
Page 194 SCSI Output Control Latch (SOCL) SCSI Output Data Latch (SODL) registers regardless of whether the LSI53C1000 is conﬁgured as a target or initiator. Note: Do not set this bit during normal operation, since it could cause contention on the SCSI bus. It is included for diagnostic purposes only.
Page 195 Reserved [2:1] SCSI Low Level Mode Setting this bit places the LSI53C1000 in the low level mode. In this mode, no DMA operations occur and no SCRIPTS execute. Arbitration and selection may be performed by setting the start sequence bit as described...
Page 196 Chapter 2, “Functional Description,” operation of the SCSI clock quadrupler. Disable Single Initiator Response If this bit is set, the LSI53C1000 ignores all bus-initiated selection attempts that employ the single-initiator option from SCSI-1. In order to select the LSI53C1000 while this bit is set, the LSI53C1000 SCSI ID and the initiator’s...
Page 197 DIFFSENS signal. These voltage windows indicate LVD, SE, or HVD operation. The bit values are deﬁned in the following table. When the HVD mode is detected, all of the LSI53C1000 3-state outputs go to the high impedance state. SCSI Registers...
Page 198 SMODE [1:0] Operating Mode Reserved High Impedance State LVD SCSI Reserved [5:0] Register: 0x53 Current Inbound SCSI Offset (CSO) Read Only CSO5 CSO4 CSO3 CSO2 CSO1 CSO0 Reserved [7:6] CSO[5:0] Current SCSI Offset [5:0] These bits indicate the SCSI offset for synchronous inbound transfers.
Page 199 WSR bit is cleared and Phase Mismatch Jump Address Two (PMJAD2) when the WSR bit is set. When this bit is set, the LSI53C1000 will use Phase Mismatch Jump Address One (PMJAD1) Data-Out (Data-Out, Command, Message-Out) transfers Phase Mismatch Jump Address Two (PMJAD2) Data-In (Data-In, Status, Message-In) transfers.
Page 200 phase referred to here is the phase encoded in the block move SCRIPTS instruction, not the phase on the SCSI bus that caused the phase mismatch. ENNDJ Enable Jump On Nondata Phase Mismatches This bit controls whether or not a jump is taken during a nondata phase mismatch (Message-In, Message-Out, Status, or Command).
Page 201 NOT be set for normal operation. DIS64MAS Disable 64-bit Master Operation Setting this bit causes the LSI53C1000 to no longer request 64-bit master data transfers. If this bit is set, 64-bit data transfers will be disabled for all master transactions.
Page 202 DMA Next Address 64 (DNAD64) to provide 40-bit addressing capability. This bit will only function if the EN64TIBMV bit is set. Index Mode 0 (64TIMOD clear) table entry format: [31:29] [28:24] [23:0] Reserved Sel Index Byte Count Source/Destination Address [31:0] Index Mode 1 (64TIMOD set) table entry format: [31:24] [23:0]...
Page 203 receiving data using programmed I/O. This register can also be used for diagnostic testing or in the low level mode. The power-up value of this register is indeterminate. If the chip is in wide mode (SCSI Control Three (SCNTL3), bit 3 is set) and SCSI Bus Data Lines (SBDL) register is read, both byte lanes are checked for parity regardless of phase.
Page 204 DSKEW[1:0] Setup Data Skew Control [3:2] These bits control the amount of skew between the SCSI REQ/ACK signal and the SCSI data signals during setup. The skew is affected only if the ENDSKEW bit is set. Note: These bits are used for Ultra160 SCSI Domain Validation only and should not be set during normal data transfer operations.
Page 205 mode, bits [12:0] of SCRATCH B will always return zeros. Writes to the SCRATCH B register have no effect. Resetting the PCI Conﬁguration Info Enable bit causes the SCRATCH B register to return to normal operation. Registers: 0x60–0x9F Scratch Registers C–R (SCRATCHC–SCRATCHR) Read/Write These are general purpose user deﬁnable scratch pad registers.
Page 206 Registers: 0xA4–0xA7 Memory Move Write Selector (MMWS) Read/Write MMWS MMWS Memory Move Write Selector [31:0] This register supplies AD[63:32] during data write operations during Memory-to-Memory Moves and absolute address STORE operations. A special mode of this register can be enabled by setting the PCI Conﬁguration Info Enable bit in the Chip Test Two (CTEST2)
Page 207 Writes to the SCRIPT Fetch Selector (SFS) register are unaffected. Clearing the PCI Conﬁguration Info Enable bit causes the SFS register to return to normal operation. Registers: 0xAC–0xAF DSA Relative Selector (DRS) Read/Write DSA Relative Selector [31:0] This register supplies AD[63:32] during Table Indirect Fetches and Load and Store Data Structure Address (DSA)
Page 208 Registers: 0xB4–0xB7 Dynamic Block Move Selector (DBMS) Read/Write DBMS DBMS Dynamic Block Move Selector [31:0] This register supplies AD[63:32] during block move operations, reads, or writes. This register is used only during 64-bit direct BMOV instructions. It is reloaded with the upper 32-bit data address upon execution of 64-bit direct BMOVs.
Page 209 DT transfers as it affects data hold to the DT edge. Setting this bit reduces the synchronous transfer send rate but does not reduce the transfer rate at which the LSI53C1000 can receive inbound REQs, ACKs or data. Refer to Table 4.4 Table 4.5...
Page 210 ST and DT transfers as it affects data hold to the ST edge. Setting this bit reduces the synchronous send transfer rate but does not reduce the transfer rate at which the LSI53C1000 can receive inbound REQs, ACKs or data. Refer to Table 4.4 Table 4.5...
Page 211 Note: The receive rate is independent of the settings of the XCLKS_DT, XCLKS_ST, XCLKH_DT, and XCLKH_ST bits. Synchronous Send Rate Calculation The synchronous send rate, in megatransfers/s, can be calculated using the following formula: Input Clock Rate Send Rate (DT) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ...
Page 212: Single Transition Transfer Waveforms
Figure 4.1 Single Transition Transfer Waveforms REQ/ACK DATA XCLKS_ST = 0 XCLKH_ST = 0 REQ/ACK DATA XCLKS_ST = 1 XCLKH_ST = 0 REQ/ACK DATA XCLKS_ST = 0 XCLKH_ST = 1 REQ/ACK DATA XCLKS_ST = 1 1. CLK = SCLK/SCF Divisor XCLKH_ST = 1 4-102 Registers...
Page 213: Dt Transfer Waveforms (Xclks Examples)
Figure 4.2 DT Transfer Waveforms (XCLKS Examples) REQ/ACK DATA XCLKS_DT = 0/XCLKS_ST = 0 XCLKH_DT = 0/XCLKH_ST = 0 REQ/ACK DATA XCLKS_DT = 0/XCLKS_ST = 1 XCLKH_DT = 0/XCLKH_ST = 0 REQ/ACK DATA XCLKS_DT = 1/XCLKS_ST = 0 XCLKH_DT = 0/XCLKH_ST = 0 REQ/ACK DATA XCLKS_DT = 1/XCLKS_ST = 1...
Page 214: Dt Transfer Waveforms (Xclkh Examples)
Figure 4.3 DT Transfer Waveforms (XCLKH Examples) REQ/ACK DATA XCLKS_DT = 0 / XCLKS_ST = 0 XCLKH_DT = 1 / XCLKH_ST = 0 REQ/ACK DATA XCLKS_DT = 0 / XCLKS_ST = 0 XCLKH_DT = 0 / XCLKH_ST = 1 REQ/ACK DATA XCLKS_DT = 0 / XCLKS_ST = 0 XCLKH_DT = 1 / XCLKH_ST = 1...
Page 215: Dt Transfer Rates
Table 4.4 DT Transfer Rates Clock Diviso Number Base Period Receive Rate Send Rate (MHz) Xclks (ns) (Megatransfers/s) (Megatransfers/s) 6.25 80.00 80.00 6.25 80.00 64.00 6.25 80.00 53.33 6.25 80.00 45.71 6.25 80.00 40.00 9.38 53.33 53.33 9.38 53.33 42.67 9.38 53.33 35.56...
Page 216: Single Transition Transfer Rates
Table 4.4 DT Transfer Rates (Cont.) Clock Diviso Number Base Period Receive Rate Send Rate (MHz) Xclks (ns) (Megatransfers/s) (Megatransfers/s) 25.00 20.00 10.00 37.50 13.33 13.33 37.50 13.33 10.67 37.50 13.33 8.89 37.50 13.33 7.62 37.50 13.33 6.67 50.00 10.00 10.00 50.00 10.00...
Page 217 Table 4.5 Single Transition Transfer Rates (Cont.) Clock Diviso Number Base Period Receive Rate Send Rate (MHz) Xclks (ns) (Megatransfers/s) (Megatransfers/s) 12.50 20.00 16.00 12.50 20.00 13.33 18.75 13.33 13.33 18.75 13.33 10.67 18.75 13.33 8.89 25.00 10.00 10.00 25.00 10.00 8.00 25.00...
Page 218 Register: 0xBD Reserved This register is reserved. Register: 0xBE AIP Control Zero (AIPCNTL0) Read Only AIPERR_LIVE AIPERR PARITYERR Reserved [7:3] AIPERR_LIVE AIP Error Status Live This bit represents the live error status for the AIP checking logic. A high indicates an error while low indicates no error.
Page 219 PARITYERR Parity Error Status This bit represents the error status for the parity error. This bit is set upon a parity error and clears when the interrupt clears. Register: 0xBF AIP Control One (AIPCNTL1) Read/Write DISAIP RAIPERR FBAIP Reserved [7:4] DISAIP Disable AIP Code Generation When set, this bit disables AIP code generation on the...
Page 220 Registers: 0xC0–0xC3 Phase Mismatch Jump Address One (PMJAD1) Read/Write PMJAD1 PMJAD1 Phase Mismatch Jump Address One [31:0] This register contains the 32-bit address that is jumped to upon a phase mismatch. Depending upon the state of the PMJCTL bit, this address is either used during an outbound (Data-Out, Command, Message-Out) phase mismatch (PMJCTL = 0) or when the WSR bit is cleared (PMJCTL = 1).
Page 221 Registers: 0xC8–0xCB Remaining Byte Count (RBC) Read/Write Remaining Byte Count [31:0] This register contains the byte count that remains for the BMOV that was executing when the phase mismatch occurred. In the case of Direct or Indirect BMOV instructions, the upper byte of this register also contains the opcode of the BMOV that was executing.
Page 222 In the case of a SCSI data receive, if there is a byte in SCSI Wide Residue (SWIDE) register then this address points to the location where that byte must be stored. The SWIDE byte must be manually written to memory and this address must be incremented prior to updating any scatter/gather entry.
Page 223 Registers: 0xD4–0xD7 Instruction Address (IA) Read/Write Instruction Address [31:0] This register always contains the address of the BMOV instruction that was executing when the phase mismatch occurred. This value will always match the value in the Entry Storage Address (ESA) except in the case of a Table Indirect BMOV in which case the ESA will have the address of the Table Indirect entry and this register points...
Page 224 determine the correct address to start fetching data from after a phase mismatch, this byte is not counted for this BMOV. It is included in the previous BMOV’s byte count. Register: 0xDB Reserved This register is reserved. Registers: 0xDC–0xDF Cumulative SCSI Byte Count (CSBC) Read/Write CSBC CSBC...
Page 225 DCRCC Disable CRC Checking Setting this bit causes the internal logic not to check or report CRC errors during Ultra160 transfers. The LSI53C1000 continues to calculate and send CRCs as requested by the target according to the SPI-3 speciﬁcation. DCRCPC...
Page 226 Register: 0xE3 CRC Control One (CRCCNTL1) Read/Write CRCERR ENAS TSTSD TSTCHK TSTADD CRCDSEL CRCERR CRC Error This bit indicates whether or not a CRC error has been detected during a DT Data-In SCSI transfer. This bit is set independent of the DCRCC bit. To clear this condition, either write this bit to a 1 or read the SIST0 and SIST1 registers.
Page 227 CRCDSEL CRC Data Register Selector [1:0] These bits control the data that is visible in the CRC Data (CRCD) register. Registers: 0xE4–0xE7 CRC Data (CRCD) Read/Write CRCD The value in this register is dependent on the setting of the CRCDSEL bits in the CRC Control One (CRCCNTL1) register.
Page 228 If CRCDSEL = 0b11, this register contains the saved bad CRC value that was calculated when a CRC error was detected. After a CRC error is detected, this register is not overwritten until the error condition is cleared. Registers: 0xE8–0xEF Reserved This register is reserved.
Page 229 Registers: 0xF4–0xFF Reserved This register is reserved. 4.3 SCSI Shadow Registers Note: For more information concerning shadow registers, refer to Chip Test Four (CTEST4), Scratch Register A (SCRATCHA), Chip Control Two (CCNTL2), Scratch Regis- ter B (SCRATCHB), Memory Move Read Selector (MMRS), Memory Move Write Selector (MMWS), and...
Page 230 Register: 0x42 Shadowed SCSI SGE Status 0 Read/Write This register contains the individual status bits which cause a SGE SCSI interrupt. These bits correspond to the SGE conditions described in the SIST0 register description. Unlike the other registers in the device, these bits must be set to one to clear the condition.
Page 231 behind the SCSI Interrupt Status One (SIST1) register. It can be accessed by setting bit 7, the Enable Shadowed SGE Register (ShSGE) bit, in the Chip Control Two (CCNTL2) register. Reserved [7:6] PNCRC Pad Request with no CRC Request Following FCRC Force CRC DTST...
Page 232 Registers: 0xA0–0xA3 Shadowed Memory Move Read Selector (MMRS) Read/Write MMRS MMRS Shadowed Memory Move Read Selector [31:0] When the PCI Conﬁguration Info Enable bit in the Chip Test Two (CTEST2) register is set, the MMRS register is placed in the shadow mode. In this mode, the Memory Move Read Selector (MMRS) register returns bits [31:0]...
Page 233 Registers: 0xA8–0xAB Shadowed SCRIPT Fetch Selector (SFS) Read/Write Shadowed SCRIPT Fetch Selector [31:0] When the PCI Conﬁguration Info Enable bit in the Chip Test Two (CTEST2) register is set, the SCRIPT Fetch Selector register is placed in shadow mode. In this mode, bits [23:16] of this register return the PCI Revision ID (RID)
Page 234 4-124 Registers...
Page 235 Chapter 5 SCSI SCRIPTS Instruction Set After power-up and initialization, the LSI53C1000 can operate in the low level register interface mode, or use SCSI SCRIPTS. With the low level register interface, the user has access to the DMA control logic and the SCSI bus control logic. An external processor has access to the SCSI bus signals and the low level DMA signals, which allow creation of complicated board level test algorithms.
Page 236 Once an interrupt is generated, the LSI53C1000 halts all operations until the interrupt is serviced. Then, the start address of the next SCRIPTS instruction is written to the DMA SCRIPTS Pointer (DSP) register to restart the automatic fetching and execution of instructions.
Page 237: Sample Operation
LSI53C1000 requests use of the PCI bus again to transfer the data. • When the LSI53C1000 is granted the PCI bus, it executes (as a bus master) a burst transfer (programmable size) of data, decrements the internally stored remaining byte count, increments the address pointer, and then releases the PCI bus.
Page 238: Block Move Instructions
In this manner, the LSI53C1000 performs scatter/gather operations on data without requiring help from the host program, generating a host interrupt, or programming of an external DMA controller. Figure 5.1 provides an overview of SCRIPTS operation.
Page 239: First Dword
SCSI bus, SIOM controls whether that data comes from the I/O or memory space. When data is moved off of the SCSI bus, DIOM controls whether that data goes to the I/O or memory space. 5.2.1 First Dword This section describes the structure of the ﬁrst SCSI SCRIPTS Dword. Bits [31:24] are loaded into the DMA Command register while bits [23:0]...
Page 240 Indirect When set, the 32-bit user data start address for the Block Move is the address of a pointer to the actual data buffer address. The value at the 32-bit start address is loaded into the chip’s DMA Next Address (DNAD) register using a third Dword fetch (4-byte transfer across the host computer bus).
Page 241 For a MOVE instruction, the 24-bit byte count is fetched from system memory. Then the 32-bit physical address is brought into the LSI53C1000. Execution of the move begins at this point. SCRIPTS can directly execute operating system I/O data structures, saving time at the beginning of an I/O operation.
Page 242 64-Bit Addressing If the Enable 64-bit Table Indirect Block Move (EN64TIBMV) bit is cleared, table indirect block moves remain as 2 Dword opcodes plus a 2 Dword table entry. The upper 32 bits of the address are copied from the Static Block Move Selector (SBMS) when performing data transfers during block move operations.
Page 243 Table Indirect block moves upper 32-bit address locations: Upper 32-Bit Data EN64TIBMV 64TIMOD Address Comes From SBMS SBMS ScratchC–J, MMWS, MMRS, SFS, DRS, SBMS, DBMS 1st Table Entry Dword bits [31:24] (40-bit addressing only) Table Indirect Index mode mapping: Index Value Selector Used 0x00 Scratch C...
Page 244 Target Mode OPC Instruction Deﬁned MOVE/MOVE64 CHMOV/CHMOV64 The LSI53C1000 veriﬁes that it is connected to the SCSI bus as a target before executing this instruction. The LSI53C1000 asserts the SCSI phase signals (SMSG/, SC_D/, and SI_O/) as deﬁned by the Phase Field bits in the instruction.
Page 245 Instruction Deﬁned CHMOV/CHMOV64 MOVE/MOVE64 The LSI53C1000 veriﬁes that it is connected to the SCSI bus as an initiator before executing this instruction. The LSI53C1000 waits for an unserviced phase to occur. An unserviced phase is deﬁned as any phase (with SREQ/ asserted) for which the LSI53C1000 has not yet transferred data by responding with a SACK/.
Page 246 Set ATN instruction), the LSI53C1000 deasserts SATN/ during the ﬁnal SREQ/SACK/ handshake. When the LSI53C1000 is performing a block move for Message-In phase, it does not deassert the SACK/ signal for the last SREQ/SACK/ handshake. Clear the SACK/ signal using the Clear SACK I/O instruction.
Page 247: Second Dword
This process is repeated until the DBC register is decremented to zero. At this time, the LSI53C1000 fetches the next instruction. If bit 28 is set, indicating table indirect addressing, this ﬁeld is not used. The byte count is instead fetched from...
Page 248: Third Dword
[31:30] OPC[2:0] Opcode [29:27] The following Opcode bits have different meanings, depending on whether the LSI53C1000 is operating in the initiator or target mode. Opcode selections 0b101– 0b111 are considered Read/Write instructions, and are described in Section 5.4, “Read/Write Instructions.”...
Page 249 32-bit jump address ﬁeld stored in the DMA Next Address (DNAD) register. Manually set the LSI53C1000 to the initiator mode if it is reselected, or to the target mode if it is selected. Disconnect Instruction The LSI53C1000 disconnects from the SCSI bus by deasserting all SCSI signal outputs.
Page 250 32-bit jump address ﬁeld stored in the DMA Next Address (DNAD) register. Manually set the LSI53C1000 to the initiator mode when it is reselected. If the CPU sets the SIGP bit in the Interrupt Status Zero...
Page 251 DMA Next Address (DNAD) register. Manually set the LSI53C1000 to the initiator mode if it is reselected, or to the target mode if it is selected. If the Select with SATN/ ﬁeld is set, the SATN/ signal is asserted during the selection phase.
Page 252 If the CPU sets the SIGP bit in the Interrupt Status Zero (ISTAT0) register, the LSI53C1000 aborts the Wait Reselect instruction and fetches the next instruction from the address pointed to by the 32-bit jump address ﬁeld stored in the DMA Next Address (DNAD) register.
Page 253 generate the address of the required data. Both positive and negative offsets are allowed. A subsequent fetch from that address brings the data values into the chip. SCRIPTS can directly execute operating system I/O data structures, saving time at the beginning of an I/O operation.
Page 254 Select with ATN/ This bit speciﬁes whether SATN/ is asserted during the selection phase when the LSI53C1000 is executing a Select instruction. When operating in the initiator mode, set this bit for the Select instruction. If this bit is set on any other I/O instruction, an illegal instruction interrupt is generated.
Page 255 This bit is used in conjunction with a Set or Clear instruction to set or clear the target mode. Setting this bit with a Set instruction conﬁgures the LSI53C1000 as a target device (this sets bit 0 of the SCSI Control Zero (SCNTL0) register).
Page 256: Second Dword
Since SATN/ is an initiator signal, it is not asserted on the SCSI bus unless the LSI53C1000 is operating as an initiator. The Set/Clear SCSI ACK/, ATN/ instructions are used after message phase Block Move operations to give the initiator the opportunity to assert attention before acknowledging the last message byte.
Page 257: Read/Write Instructions
5.4 Read/Write Instructions The Read/Write instruction supports addition, subtraction, and comparison of two separate values within the chip. It performs the desired operation on the speciﬁed register and the SCSI First Byte Received (SFBR) register and stores the result back to the speciﬁed register or to the SFBR.
Page 258: Second Dword
It is possible to change register values from SCRIPTS in read-modify-write cycles or move to/from SCSI First Byte Received (SFBR) cycles. A[6:0] selects an 8-bit source/destination register within the LSI53C1000. IMMD Immediate Data [15:8] This 8-bit value is used as a second operand in logical and arithmetic functions.
Page 259: Move To/From Sfbr Cycles
5.4.4 Move To/From SFBR Cycles All operations are read-modify-writes. However, two registers are involved, one of which is always the SCSI First Byte Received (SFBR). The possible functions of this instruction are: • Write one byte (value contained within the SCRIPTS instruction) into any chip register.
Page 260 Table 5.1 Read/Write Instructions (Cont.) Opcode 111 Opcode 110 Opcode 101 Operator Read Modify Write Move to SFBR Move from SFBR XOR data with register and XOR data with register and XOR data with SFBR and place the result in the same place the result in the SCSI place the result in the...
Page 261: Transfer Control Instructions
Interrupt Reserved Jump Instruction The LSI53C1000 can do a true/false comparison of the ALU carry bit, or compare the phase and/or data as deﬁned by the Phase Compare, Data Compare and True/False bit ﬁelds. If the comparisons are true, it loads...
Page 262 DMA SCRIPTS Pointer Save (DSPS) register. The DSP register now contains the address of the next instruction. If the comparisons are false, the LSI53C1000 fetches the next instruction from the address pointed to by the SCRIPTS Pointer (DSP) register, leaving the instruction pointer unchanged.
Page 263 It does not generate an interrupt if a Return instruction is executed without previously executing a Call instruction. If the comparisons are false, the LSI53C1000 fetches the next instruction from the address pointed to by the SCRIPTS Pointer (DSP) register and the instruction pointer is not modiﬁed.
Page 264 SCSI bus. The following table describes the possible combinations and their corresponding SCSI phase. These bits are only valid when the LSI53C1000 is operating in the initiator mode. Clear these bits when the LSI53C1000 is operating in the target mode.
Page 265 (Interrupt Status Zero (ISTAT0), bit 2) is asserted. Jump If True/False This bit determines whether the LSI53C1000 branches when a comparison is true or when a comparison is false. This bit applies to phase compares, data compares, and carry tests. If both the Phase Compare and Data Compare bits are set, then both compares must be true to branch on a true condition.
Page 266 SCSI SATN/ signal. Wait For Valid Phase If the Wait for Valid Phase bit is set, the LSI53C1000 waits for a previously unserviced phase before comparing the SCSI phase and data.
Page 267: Second Dword
This 32-bit ﬁeld contains the address of the next instruction to fetch when a jump is taken. Once the LSI53C1000 fetches the instruction from the address pointed to by these 32-bits, this address is incremented by 4, loaded into the DMA SCRIPTS Pointer (DSP) register and becomes the current instruction pointer.
Page 268: Memory Move Instructions
Memory Move Write Selector (MMWS) register. Allowing the LSI53C1000 to perform memory moves frees the system processor for other tasks and moves data at higher speeds than available from current DMA controllers. Up to 16 Mbytes may be transferred with one instruction.
Page 269: Read/Write System Memory From A Script
These bits are reserved and must be zero. If any of these bits are set, an illegal instruction interrupt occurs. No Flush When this bit is set, the LSI53C1000 performs a Memory Move without ﬂushing the prefetch unit. When this bit is cleared, the Memory Move instruction automatically ﬂushes the prefetch unit.
Page 270: Second Dword
Memory Move. However, it can be loaded using SCRIPTS Read/Write operations. To load the SFBR with a byte stored in system memory, ﬁrst move the byte to an intermediate LSI53C1000 register (for example, a SCRATCH register), and then to the...
Page 271: Load And Store Instructions
Figure 5.14 Memory Move Instructions - Third Dword 24 23 16 15 TEMP Register TEMP Register [31:0] These bits contain the destination address for the Memory Move. If the destination address is in the 64-bit address space, the bits will be contained in the Memory Move Write Selector (MMWS) register.
Page 272: First Dword
excluding RAM and ROM. If it does, a PCI read/write cycle occurs (the data does not actually transfer to/from the chip), and the chip issues an interrupt (Illegal Instruction Detected) immediately following. Bits A1, A0 Number of Bytes Allowed to Load/Store One, two, three or four One, two, or three One or two...
Page 273: Second Dword
Reserved [27:26] No Flush (Store instruction only) When this bit is set, the LSI53C1000 performs a Store without ﬂushing the prefetch unit. When this bit is cleared, the Store instruction automatically ﬂushes the prefetch unit. Use No Flush if the source and destination are not within four instructions of the current Store instruction.
Page 274: Load And Store Instructions - Second Dword
Figure 5.16 Load and Store Instructions - Second Dword 24 23 16 15 DSPS Register - Memory I/O Address/DSA Offset 24 23 16 15 MMRS/MMWS Register Memory I/O Address / DSA Offset [31:0] This is the actual memory location of where to load/store, or the offset from the Data Structure Address (DSA) register value.
Page 275: Chapter 6 Speciﬁcations
Section 6.4, “PCI and External Memory Interface Timing Diagrams” • Section 6.5, “SCSI Timing Diagrams” • Section 6.6, “Package Drawings” 6.1 DC Characteristics This section of the manual describes the LSI53C1000 DC characteristics. Tables through 6.12 give current and voltage speciﬁcations. Figures are driver schematics.
Page 276: Absolute Maximum Stress Ratings
Table 6.1 Absolute Maximum Stress Ratings Symbol Parameter Unit Test Conditions −55 °C Storage temperature – −0.5 Supply voltage – −0.3 Input voltage 5.55 – −5.5 Input voltage PCI pins 11.0 – IN-PCI ±150 Latch-up current – – °C Lead temperature –...
Page 277: Lvd Driver
Table 6.3 LVD Driver SCSI Signals —SD[15:0], SDP[1:0], SREQ/, SACK/, SMSG/, SIO/, SCD/, SATN/, SBSY/, SSEL/, SRST/ Symbol Parameter Units Test Conditions −9.6 −14.4 Source (+) current Asserted state − Sink (−) current 14.4 Asserted state Source (+) current Negated state −...
Page 278: Lvd Receiver
Figure 6.2 LVD Receiver − − − − Table 6.5 DIFFSENS SCSI Signals Symbol Parameter Unit Test Conditions HVD sense voltage 5.05 Note 1 LVD sense voltage Note 1 −0.35 SE sense voltage Note 1 −10 µA 3-state leakage = 3 Max 1.
Page 279: Ma Bidirectional Signals—Gpio0_Fetch Gpio1_Master/, Gpio2, Gpio3, Gpio4
Table 6.7 8 mA Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/, GPIO2, GPIO3, GPIO4 Symbol Parameter Unit Test Conditions Input high voltage 5.55 – −0.3 Input low voltage – −8 mA Output high voltage Output low voltage 8 mA −10 µA 3-state leakage – µA Pull down current –...
Page 280: Frame/, Irdy/, Trdy/, Devsel/, Stop/, Perr Par, Par64, Req64/, Ack64/
Table 6.10 8 mA PCI Bidirectional Signals—AD[63:0], C_BE[7:0]/, FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR, PAR64, REQ64/, ACK64/ Symbol Parameters Unit Test Conditions Input high voltage 0.5 V +0.5 – −0.5 Input low voltage 0.3 V – −8 mA Output high voltage 0.9 V Output low voltage 0.1 V...
Page 281: Tolerant Technology Electrical Characteristics
6.2 TolerANT Technology Electrical Characteristics The LSI53C1000 features TolerANT technology, which includes active negation on the SCSI drivers and input signal ﬁltering on the SCSI receivers. Active negation actively drives the SCSI Request, Acknowledge, Data, and Parity signals HIGH rather than allowing them to be passively pulled up by terminators.
Page 282: Rise And Fall Time Test Condition
Table 6.13 TolerANT Technology Electrical Characteristics for SE SCSI Signals (Cont.) Symbol Parameter Units Test Conditions Capacitance per pin – PQFP Rise time, 10% to 90% 14.7 Figure 6.3 Fall time, 90% to 10% 17.2 Figure 6.3 Slew rate LOW to HIGH mV/ns Figure 6.3 Slew rate HIGH to LOW...
Page 283: Hysteresis Of Scsi Receivers
Figure 6.5 Hysteresis of SCSI Receivers Input Voltage (Volts) Figure 6.6 Input Current as a Function of Input Voltage 14.4 V 8.2 V −0.7 V HIGH-Z OUTPUT −20 ACTIVE −40 −4 Input Voltage (Volts) TolerANT Technology Electrical Characteristics...
Page 284: Output Current As A Function Of Output Voltage
Figure 6.7 Output Current as a Function of Output Voltage −200 −400 −600 −800 Output Voltage (Volts) Output Voltage (Volts) 6-10 Speciﬁcations...
Page 285: Ac Characteristics
6.3 AC Characteristics The AC characteristics described in this section apply over the entire range of operating conditions (refer to Section 6.1, “DC Characteristics”). Chip timing is based on simulation at worst case voltage, temperature, and processing. Timing was developed with a load capacitance of 50 pF. Table 6.14 Figure 6.8 provide external clock timing data.
Page 286: Reset Input
Table 6.15 Figure 6.9 provide Reset Input timing data. Table 6.15 Reset Input Symbol Parameter Units Reset pulse width – Reset deasserted setup to CLK HIGH – MAD setup time to CLK HIGH (for conﬁguring – the MAD bus only) MAD hold time from CLK HIGH (for conﬁguring –...
Page 287: Pci And External Memory Interface Timing Diagrams
6.38 represent signal activity when the LSI53C1000 accesses the PCI bus. This section includes timing diagrams for access to three groups of memory conﬁgurations. The ﬁrst group applies to Target Timing. The second group applies to Initiator Timing. The third group applies to External Memory Timing.
Page 288: Target Timing
– Operating Register/SCRIPTS RAM Write, 32 Bits – Operating Register/SCRIPTS RAM Write, 64 Bits • Initiator Timing – Nonburst Opcode Fetch, 32-Bit Address and Data – Burst Opcode Fetch, 32-Bit Address and Data – Back to Back Read, 32-Bit Address and Data –...
Page 289: Pci Conﬁguration Register Read
(Driven by Master-Addr; LSI53C1000-Data) C_BE[3:0]/ Byte Enable (Driven by Master) (Driven by Master-Addr; LSI53C1000-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C1000) STOP/ (Driven by LSI53C1000) DEVSEL/ (Driven by LSI53C1000) IDSEL (Driven by Master) PCI and External Memory Interface Timing Diagrams 6-15...
Page 290: Pci Conﬁguration Register Write
(Driven by Master) Addr In AD[31:0] Data In (Driven by Master) C_BE[3:0]/ Byte Enable (Driven by Master) (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C1000) STOP/ (Driven by LSI53C1000) DEVSEL/ (Driven by LSI53C1000) IDSEL (Driven by Master) 6-16 Speciﬁcations...
Page 291: Operating Registers/Scripts Ram Read, 32 Bits
AD[31:0] Data (Driven by Master-Addr; LSI53C1000-Data) C_BE[3:0]/ Byte Enable (Driven by Master) (Driven by Master-Addr; LSI53C1000-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C1000) STOP/ (Driven by LSI53C1000) DEVSEL/ (Driven by LSI53C1000) PCI and External Memory Interface Timing Diagrams 6-17...
Page 292: Operating Register/Scripts Ram Read, 64 Bits
Table 6.20 Operating Register/SCRIPTS RAM Read, 64 Bits 66 MHz PCI 33 MHz PCI Symbol Parameter Unit Shared signal input setup time – – Shared signal input hold time – – CLK to shared signal output valid 6-18 Speciﬁcations...
Page 293: Operating Register/Scripts Ram Read, 64 Bits
Figure 6.14 Operating Register/SCRIPTS RAM Read, 64 Bits (Driven by System) REQ64/ (Driven by Master) ACK64/ (Driven by LSI53C1000) FRAME/ (Driven by Master) AD[31:0] Addr Addr Data (Driven by Master-Addr; LSI53C1000-Data) C_BE[3:0]/ Dual Byte Enable (Driven by Master) Addr AD[63:32] (Driven by Master-Addr;...
Page 294: Operating Register/Scripts Ram Read, 32 Bits
Table 6.21 Operating Register/SCRIPTS RAM Read, 32 Bits 66 MHz PCI 33 MHz PCI Symbol Parameter Unit Shared signal input setup time – – Shared signal input hold time – – CLK to shared signal output valid 6-20 Speciﬁcations...
Page 295: Operating Register/Scripts Ram Write, 32 Bits
Addr In AD[31:0] Data In (Driven by Master) C_BE[3:0]/ Byte Enable (Driven by Master) (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C1000) STOP/ (Driven by LSI53C1000) DEVSEL/ (Driven by LSI53C1000) PCI and External Memory Interface Timing Diagrams 6-21...
Page 296: Operating Register/Scripts Ram Write, 64 Bits
Table 6.22 Operating Register/SCRIPTS RAM Write, 64 Bits 66 MHz PCI 33 MHz PCI Symbol Parameter Unit Shared signal input setup time – – Shared signal input hold time – – CLK to shared signal output valid 6-22 Speciﬁcations...
Page 297: Operating Register/Scripts Ram Write, 64 Bits
Figure 6.16 Operating Register/SCRIPTS RAM Write, 64 Bits (Driven by System) REQ64/ (Driven by Master) ACK64/ (Driven by LSI53C1000) FRAME/ (Driven by Master) AD[31:0] Addr Addr Data In (Driven by Master) C_BE[3:0]/ Dual Byte Enable (Driven by Master) Addr AD[63:32]...
Page 298: Initiator Timing
6.4.2 Initiator Timing Tables 6.23 through 6.30 and ﬁgures 6.17 6.24 describe Initiator timing. Table 6.23 Nonburst Opcode Fetch, 32-Bit Address and Data 66 MHz PCI 33 MHz PCI Symbol Parameter Unit Shared signal input setup time – – Shared signal input hold time –...
Page 299: Nonburst Opcode Fetch, 32-Bit Address And Data
Figure 6.17 Nonburst Opcode Fetch, 32-Bit Address and Data (Driven by System) REQ64/ (Driven by LSI53C1000) ACK64/ (Driven by LSI53C1000) GPIO0_FETCH/ (Driven by LSI53C1000) GPIO1_MASTER/ (Driven by LSI53C1000) REQ/ (Driven by LSI53C1000) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C1000)
Page 300: Burst Opcode Fetch, 32-Bit Address And Data
Table 6.24 Burst Opcode Fetch, 32-Bit Address and Data 66 MHz PCI 33 MHz PCI Symbol Parameter Unit Shared signal input setup time – – Shared signal input hold time – – CLK to shared signal output valid Side signal input setup time –...
Page 301: Burst Opcode Fetch, 32-Bit Address And Data
Figure 6.18 Burst Opcode Fetch, 32-Bit Address and Data (Driven by System) REQ64/ (Driven by LSI53C1000) ACK64/ (Driven by LSI53C1000) GPIO0_FETCH/ (Driven by LSI53C1000) GPIO1_MASTER/ (Driven by LSI53C1000) REQ/ (Driven by LSI53C1000) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C1000)
Page 302: Back To Back Read, 32-Bit Address And Data
Table 6.25 Back to Back Read, 32-Bit Address and Data 66 MHz PCI 33 MHz PCI Symbol Parameter Unit Shared signal input setup time – – Shared signal input hold time – – CLK to shared signal output valid Side signal input setup time –...
Page 303: Back To Back Read, 32-Bit Address And Data
Figure 6.19 Back to Back Read, 32-Bit Address and Data (Driven by System) REQ64/ (Driven by LSI53C1000) ACK64/ (Driven by LSI53C1000) GPIO0_FETCH/ (Driven by LSI53C1000) GPIO1_MASTER/ (Driven by LSI53C1000) REQ/ (Driven by LSI53C1000) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C1000)
Page 304: Back To Back Write, 32-Bit Address And Data
Table 6.26 Back to Back Write, 32-Bit Address and Data 66 MHz PCI 33 MHz PCI Symbol Parameter Unit Shared signal input setup time – – Shared signal input hold time – – CLK to shared signal output valid Side signal input setup time –...
Page 305: Back To Back Write, 32-Bit Address And Data
Figure 6.20 Back to Back Write, 32-Bit Address and Data (Driven by System) REQ64/ (Driven by LSI53C1000) ACK64/ (Driven by LSI53C1000) GPIO0_FETCH/ (Driven by LSI53C1000) GPIO1_MASTER/ (Driven by LSI53C1000) REQ/ (Driven by LSI53C1000) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C1000)
Page 306: Burst Read, 32-Bit Address And Data
Table 6.27 Burst Read, 32-Bit Address and Data 66 MHz PCI 33 MHz PCI Symbol Parameter Unit Shared signal input setup time – – Shared signal input hold time – – CLK to shared signal output valid 6-32 Speciﬁcations...
Page 307: Burst Read, 32-Bit Address And Data
Figure 6.21 Burst Read, 32-Bit Address and Data (Driven by System) GPIO0_FETCH/ (Driven by LSI53C1000) GPIO1_MASTER/ (Driven by LSI53C1000) REQ/ (Driven by LSI53C1000) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C1000) Data In AD[31:0] Addr (Driven by LSI53C1000- Addr; Target-Data)
Page 308: Burst Read, 64-Bit Address And Data
Table 6.28 Burst Read, 64-Bit Address and Data 66 MHz PCI 33 MHz PCI Symbol Parameter Unit Shared signal input setup time – – Shared signal input hold time – – CLK to shared signal output valid 6-34 Speciﬁcations...
Page 309: Burst Read, 64-Bit Address And Data
Data In AD[63:32] (Driven by LSI53C1000- Hi Address Addr; Target-Data) C_BE[7:4]/ Bus CMD (Driven by LSI53C1000) PAR; PAR64 (Addr drvn by LSI53C1000;- Data drvn by Target) IRDY/ (Driven by LSI53C1000) TRDY/ (Driven by Target) STOP/ (Driven by Target) DEVSEL/ (Driven by Target)
Page 310: Burst Write, 32-Bit Address And Data
Table 6.29 Burst Write, 32-Bit Address and Data 66 MHz PCI 33 MHz PCI Symbol Parameter Unit Shared signal input setup time – – Shared signal input hold time – – CLK to shared signal output valid 6-36 Speciﬁcations...
Page 311: Burst Write, 32-Bit Address And Data
Figure 6.23 Burst Write, 32-Bit Address and Data (Driven by System) GPIO0_FETCH/ (Driven by LSI53C1000) GPIO1_MASTER/ (Driven by LSI53C1000) REQ/ (Driven by LSI53C1000) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C1000) AD[31:0] Addr Data Data (Driven by LSI53C1000) C_BE[3:0]/ (Driven by LSI53C1000)
Page 312: Burst Write, 64-Bit Address And Data
Table 6.30 Burst Write, 64-Bit Address and Data 66 MHz PCI 33 MHz PCI Symbol Parameter Unit Shared signal input setup time – – Shared signal input hold time – – CLK to shared signal output valid 6-38 Speciﬁcations...
Page 313: Burst Write, 64-Bit Address And Data
Figure 6.24 Burst Write, 64-Bit Address and Data (Driven by System) GPIO0_FETCH/ (Driven by LSI53C1000) GPIO1_MASTER/ (Driven by LSI53C1000) REQ/ (Driven by LSI53C1000) GNT/ (Driven by Arbiter) REQ64/ (Driven by LSI53C1000) ACK64/ (Driven by Target) FRAME/ (Driven by LSI53C1000) AD[31:0]...
Page 314 This page intentionally left blank. 6-40 Speciﬁcations...
Page 315: External Memory Timing
6.4.3 External Memory Timing Tables 6.31 through 6.38 and ﬁgures 6.25 through 6.34 describe External Memory timing. Table 6.31 External Memory Read 66 MHz PCI 33 MHz PCI Symbol Parameter Unit Shared signal input setup time – – Shared signal input hold time –...
Page 316: External Memory Read
(Driven by Master) TRDY/ (Driven by LSI53C1000) STOP/ (Driven by LSI53C1000) DEVSEL/ (Driven by LSI53C1000) High Order Middle Order Low Order (Addr driven by LSI53C1000; Address Address Address Data Driven by Memory) MAS1/ (Driven by LSI53C1000) MAS0/ (Driven by LSI53C1000) MCE/...
Page 317 IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C1000) STOP/ (Driven by LSI53C1000) DEVSEL/ (Driven by LSI53C1000) Data (Addr driven by LSI53C1000; Data Driven by Memory) MAS1/ (Driven by LSI53C1000) MAS0/ (Driven by LSI53C1000) MCE/ (Driven by LSI53C1000) MOE/ (Driven by LSI53C1000)
Page 318 This page intentionally left blank. 6-44 Speciﬁcations...
Page 319: External Memory Write
Table 6.32 External Memory Write Symbol Parameter Unit Shared signal input setup time – – Shared signal input hold time – – CLK to shared signal output valid Address setup to MAS/ HIGH – – Address hold from MAS/ HIGH –...
Page 320: External Memory Write
Data In (Driven by Master) C_BE[3:0]/ Byte Enable (Driven by Master) (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C1000) STOP/ (Driven by LSI53C1000) DEVSEL/ (Driven by LSI53C1000) Middle Order High Order Low Order (Driven by LSI53C1000) Address...
Page 321 (Driven by Master) AD[31:0] (Driven by Master) C_BE[3:0]/ (Driven by Master) (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C1000) STOP/ (Driven by LSI53C1000) DEVSEL/ (Driven by LSI53C1000) Data Out (Driven by LSI53C1000) MAS1/ (Driven by LSI53C1000) MAS0/...
Page 322: Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access Read Cycle
Data setup to CLK HIGH – Figure 6.27 Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access Read Cycle (Driven by System) High Order Middle Order Low Order (Addr driven by LSI53C1000; Address Address Address Data Driven by Memory) MAS1/ (Driven by LSI53C1000)
Page 323 Figure 6.27 Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access Read Cycle (Cont.) (Driven by System) Valid Read (Addr driven by LSI53C1000; Data Data Driven by Memory) MAS1/ (Driven by LSI53C1000) MAS0/ (Driven by LSI53C1000) MCE/ (Driven by LSI53C1000) MOE/...
Page 324: Access Write Cycle
MWE/ HIGH to MCE/ HIGH – Figure 6.28 Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access Write Cycle (Driven by System) Valid High Order Middle Order Low Order Write (Driven by LSI53C1000) Address Address Address Data MAS1/ (Driven by LSI53C1000) MAS0/ (Driven by LSI53C1000)
Page 325 Figure 6.28 Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access Write Cycle (Cont.) (Driven by System) Valid Write Data (Driven by LSI53C1000) MAS1/ (Driven by LSI53C1000) MAS0/ (Driven by LSI53C1000) MCE/ (Driven by LSI53C1000) MOE/ (Driven by LSI53C1000) MWE/ (Driven by LSI53C1000)
Page 326 TRDY/ (Driven by LSI53C1000) STOP/ (Driven by LSI53C1000) DEVSEL/ (Driven by LSI53C1000) Middle Order High Order Order (Addr Driven by LSI53C1000 Address Address Address Data Driven by Memory) MAS1/ (Driven by LSI53C1000) MAS0/ (Driven by LSI53C1000) MCE/ (Driven by LSI53C1000)
Page 327 TRDY/ (Driven by LSI53C1000) STOP/ (Driven by LSI53C1000) DEVSEL/ (Driven by LSI53C1000) Data In Low Order Data In (Addr Driven by LSI53C1000 Address Data Driven by Memory) MAS1/ (Driven by LSI53C1000) MAS0/ (Driven by LSI53C1000) MCE/ (Driven by LSI53C1000) MOE/...
Page 328 Addr AD[31:0] Data (Driven by Master) C_BE[3:0]/ Byte (Driven by Master) Enable (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C1000) STOP/ (Driven by LSI53C1000) DEVSEL/ (Driven by LSI53C1000) Middle Order High Order Order Data Out Address Address...
Page 329 AD[31:0] Data In (Driven by Master) C_BE[3:0]/ Byte Enable (Driven by Master) (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C1000) STOP/ (Driven by LSI53C1000) DEVSEL/ (Driven by LSI53C1000) Low Order Address Data Out (Driven by LSI53C1000) MAS1/...
Page 330 Data setup to CLK HIGH – Figure 6.31 Slow Memory (≥ 128 Kbytes) Read Cycle (Driven by System) Middle Order High Order Low Order (Addr drvn by LSI53C1000 Address Address Address Data drvn by Mem) MAS1/ (Driven by LSI53C1000) MAS0/...
Page 331 Figure 6.31 Slow Memory (≥ 128 Kbytes) Read Cycle (Cont.) (Driven by System) Valid Read (Addr driven by LSI53C1000; Data Data Driven by Memory) MAS1/ (Driven by LSI53C1000) MAS0/ (Driven by LSI53C1000) MCE/ (Driven by LSI53C1000) MOE/ (Driven by LSI53C1000)
Page 332 – Figure 6.32 Slow Memory (≥ 128 Kbytes) Write Cycle (Driven by System) Valid High Order Middle Order Low Order Write Address (Driven by LSI53C1000) Address Address Data MAS1/ (Driven by LSI53C1000) MAS0/ (Driven by LSI53C1000) MCE/ (Driven by LSI53C1000)
Page 333 Figure 6.32 Slow Memory (≥ 128 Kbytes) Write Cycle (Cont.) (Driven by System) Valid Write Data (Driven by LSI53C1000) MAS1/ (Driven by LSI53C1000) MAS0/ (Driven by LSI53C1000 MCE/ (Driven by LSI53C1000) MOE/ (Driven by LSI53C1000) MWE/ (Driven by LSI53C1000) PCI and External Memory Interface Timing Diagrams...
Page 334 Data setup to CLK HIGH – Figure 6.33 ≤ 64 Kbytes ROM Read Cycle (Driven by System) Valid Read High Order Low Order (Addr drvn by LSI53C1000; Data Address Address Data drvn by Mem) MAS1/ (Driven by LSI53C1000) MAS0/ (Driven by LSI53C1000)
Page 335 – MWE/ HIGH to MCE/ HIGH – Figure 6.34 ≤ 64 Kbytes ROM Write Cycle (Driven by System) High Order Low Order Valid Write Data (Driven by LSI53C1000) Address Address MAS1/ (Driven by LSI53C1000) MAS0/ (Driven by LSI53C1000) MCE/ (Driven by LSI53C1000)
Page 336: Scsi Timing Diagrams
6.5 SCSI Timing Diagrams Figures 6.35 through 6.40 and tables 6.39 through 6.50 describe the LSI53C1000 SCSI timing. Table 6.39 Initiator Asynchronous Send Symbol Parameter Units SACK/ asserted from SREQ/ asserted – SACK/ deasserted from SREQ/ deasserted – Data setup to SACK/ asserted –...
Page 337: Initiator Asynchronous Receive
Table 6.40 Initiator Asynchronous Receive Symbol Parameter Units SACK/ asserted from SREQ/ asserted – SACK/ deasserted from SREQ/ deasserted – Data setup to SREQ/ asserted – Data hold from SACK/ asserted – Figure 6.36 Initiator Asynchronous Receive SREQ/ n + 1 SACK/ n + 1 SD[15:0]/,...
Page 338: Target Asynchronous Receive
Table 6.42 Target Asynchronous Receive Symbol Parameter Units SREQ/ deasserted from SACK/ asserted – SREQ/ asserted from SACK/ deasserted – Data setup to SACK/ asserted – Data hold from SREQ/ deasserted – Figure 6.38 Target Asynchronous Receive SREQ/ n + 1 SACK/ n + 1 SD[15:0]/,...
Page 339: Scsi-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) Or 20.0 Mbytes (16-Bit Transfers) 40 Mhz Clock
Table 6.44 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes (16-Bit Transfers) 40 MHz Clock Symbol Parameter Units Send SREQ/ or SACK/ assertion pulse width – Send SREQ/ or SACK/ deassertion pulse width – Receive SREQ/ or SACK/ assertion pulse width –...
Page 340: Initiator And Target St Synchronous Transfer
Table 6.46 Ultra2 SCSI Transfers 40.0 Mbyte (8-Bit Transfers) or 80.0 Mbyte (16-Bit Transfers) Quadrupled 40 MHz Clock Symbol Parameter Unit Send SREQ/ or SACK/ assertion pulse width – Send SREQ/ or SACK/ deassertion pulse width – Receive SREQ/ or SACK/ assertion pulse width –...
Page 341: Scsi-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers Or 20.0 Mbytes (16-Bit Transfers) 40 Mhz Clock
Table 6.47 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes (16-Bit Transfers) 40 MHz Clock Symbol Parameter Unit Send SREQ/ assertion pulse width – Send SREQ/ deassertion pulse width – Receive SREQ/ assertion pulse width – Receive SREQ/ deassertion pulse width –...
Page 342: Mbyte (16-Bit Transfers) Quadrupled 40 Mhz Clock
Table 6.48 Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers) or 40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock (Cont.) Symbol Parameter Unit Receive data setup to SREQ/ transition – Receive data hold from SREQ/ transition – Send CRC Request Setup to SREQ/ transition –...
Page 343 Table 6.50 Ultra160 SCSI Transfers 160.0 Mbyte (16-Bit Transfers) Quadrupled 40 MHz Clock Symbol Parameter Unit Send SREQ/ assertion pulse width 11.5 – Send SREQ/ deassertion pulse width 11.5 – Receive SREQ/ assertion pulse width – Receive SREQ/ deassertion pulse width –...
Page 344 This page intentionally left blank. 6-70 Speciﬁcations...
Page 345: Package Drawings
329 Ball Grid Array (BGA). Table 6.51 Table 6.52 list all the signal names alphabetically and by BGA position. Figure 6.42 illustrates the LSI53C1000 329 BGA. Figure 6.43 illustrates the LSI53C1000 329 BGA mechanical drawing. Package Drawings 6-71...
Page 346: Lsi53C1000 329 Bga Chip - Top View
Figure 6.41 LSI53C1000 329 BGA Chip - Top View TEST_PD SD12+ SD13+ SD15+ SD0+ SD2− SD4− SD6− SDP0− SBSY+ BIAS M66EN V ENABLE66 SD13− SD15− SD0− SD1+ SD3+ SD5+ SD7+ SATN- SATN+ C TEST_ SD12− SD14− SDP1− SD1− SD2+ SD4+...
Page 347 Figure 6.41 LSI53C1000 329 BGA Chip - Top View (Cont.) SACK+ SMSG+ SC_D+ SREQ+ SD8− SD10− DIFFSENS SCLK CORE SRST− SSEL− SI_O− SD8+ SD10+ CORE CORE SACK− SMSG− SC_D− SREQ− SI_O+ SD9+ SD11+ SCAN_ TEST_ MODE SRST+ SSEL+ SD9− SD11−...
Page 348: Alphanumeric List By Signal Names
Table 6.51 Alphanumeric list by Signal Names Signal Signal Signal Signal Signal Name Name Name Name Name C_BE1/ SD10− ACK64/ C_BE2/ SD10+ C_BE3/ SD11− C_BE4/ SD11+ AD10 C_BE5/ SD12− AD11 C_BE6/ SD12+ AD12 C_BE7/ SD13− AD13 SD13+ AD14 DEVSEL/ SD14− AD15 DIFFSENS SD14+...
Page 349: Alphanumeric List By Bga Positions
Table 6.52 Alphanumeric List by BGA Positions Signal Signal Signal Signal Signal Name Name Name Name Name MAD1 AB21 SD11+ STOP/ TEST_PD AB22 C_BE3/ SERR/ SD12+ _CORE AB23 AD24 PERR/ SD13+ _CORE SCAN_MODE AD26 SD15+ _CORE TEST_HSC SD0+ C_BE6/ SD2− C_BE4/ _CORE SD4−...
Page 350: Lsi53C1000 329 Ball Grid Array (Bottom View)
Figure 6.42 LSI53C1000 329 Ball Grid Array (Bottom view) 6-76 Speciﬁcations...
Page 351: Lsi53C1000 329 Bga Mechanical Drawing
Figure 6.43 LSI53C1000 329 BGA Mechanical Drawing Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code VW. Package Drawings...
Page 352 6-78 Speciﬁcations...
Page 353: Appendix A Register Summary
Appendix A Register Summary Table A.1 lists the LSI53C1000 PCI registers by register name. Table A.1 LSI53C1000 PCI Register Map Register Name Address Read/Write Page PCI Registers Base Address Register Four (BAR4) (SCRIPTS RAM) 0x20–0x23 Read/Write 4-11 Base Address Register One (BAR1) (MEMORY) 0x14–0x17...
Page 354 Table A.1 LSI53C1000 PCI Register Map (Cont.) Register Name Address Read/Write Page Latency Timer (LT) 0x0D Read/Write Max_Lat (ML) 0x3F Read Only 4-17 Min_Gnt (MG) 0x3E Read Only 4-17 Next Item Pointer (NIP) 0x41 Read Only 4-18 Power Management Capabilities (PMC) 0x42–0x43...
Page 355: A.2 Lsi53C1000 Scsi Register Map
Table A.2 lists the LSI53C1000 SCSI registers, Phase Mismatch Jump registers, and Shadow registers by register name. Table A.2 LSI53C1000 SCSI Register Map Register Name Address Read/Write Page SCSI Registers Adder Sum Output (ADDER) 0x3C–0x3F Read Only 4-68 AIP Control One (AIPCNTL1)
Page 356 Table A.2 LSI53C1000 SCSI Register Map (Cont.) Register Name Address Read/Write Page DMA Next Address 64 (DNAD64) 0xB8–0xBB Read/Write 4-98 DMA SCRIPTS Pointer (DSP) 0x2C–0x2F Read/Write 4-60 DMA SCRIPTS Pointer Save (DSPS) 0x30–0x33 Read/Write 4-60 DMA Status (DSTAT) 0x0C Read Only...
Page 357 Table A.2 LSI53C1000 SCSI Register Map (Cont.) Register Name Address Read/Write Page SCSI Bus Control Lines (SBCL) 0x0B Read Only 4-38 SCSI Bus Data Lines (SBDL) 0x58–0x59 Read Only 4-92 SCSI Chip ID (SCID) 0x04 Read/Write 4-32 SCSI Control Four (SCNTL4)
Page 358 Table A.2 LSI53C1000 SCSI Register Map (Cont.) Register Name Address Read/Write Page SCSI Test Zero (STEST0) 0x4C Read Only 4-81 SCSI Timer One (STIME1) 0x49 Read/Write 4-79 SCSI Timer Zero (STIME0) 0x48 Read/Write 4-78 SCSI Transfer (SXFER) 0x05 Read/Write 4-33...
Page 359 Table A.2 LSI53C1000 SCSI Register Map (Cont.) Register Name Address Read/Write Page Shadow Registers Shadowed Memory Move Read Selector (MMRS) 0xA0–0xA3 Read/Write 4-122 Shadowed Memory Move Write Selector (MMWS) 0xA4–0xA7 Read/Write 4-122 Shadowed Scratch Register A (SCRATCHA) 0x34–0x37 Read/Write 4-119 Shadowed Scratch Register B (SCRATCHB) 0x5C–0x5F...
Page 360 Register Summary...
Page 361: Appendix B External Memory Interface Diagram Examples
4.7 K 27C128 D[7:0] LSI53C1000 Q[7:0] HCT374 MAS0/ Q[5:0] D[5:0] HCT374 MAS1/ Note: MAD[3:1] pulled LOW internally. MAD bus sense logic enabled for 16 Kbyte of slow memory (200 ns devices @ 66 MHz). LSI53C1000 PCI to Ultra160 SCSI Controller...
Page 362: Kbyte Interface With 150 Ns Memory
D[7:0] MAD[7:0] A[7:0] 27C512-15/ A[15:8] 28F512-15/ MAD2 4.7 K Socket LSI53C1000 D[7:0] Q[7:0] HCT374 MAS0/ Q[7:0] D[7:0] HCT374 MAS1/ Note: MAD 3, 1, 0 pulled LOW internally. MAD bus sense logic enabled for 64 Kbyte of fast memory (150 ns devices @ 66 MHz).
Page 363: Kbyte Or 1 Mbyte Interface With 150 Ns Memory
MWE/ MOE/ MCE/ D[7:0] MAD[7:0] A[7:0] 27C020-15/ A[15:8] 28F020-15/ MAD3 4.7 K Socket A[19:16] LSI53C1000 D[7:0] Q[7:0] HCT374 MAS0/ Q[7:0] D[7:0] HCT374 MAS1/ MAD[3:0] Q[3:0] D[3:0] HCT377 Note: MAD[2:0] pulled LOW internally. MAD bus sense logic enabled for 128, 256, 512 Kbytes, or 1 Mbyte of fast memory (150 ns devices @ 66 MHz).
Page 364: Kbyte Interface With 150 Ns Memory
D[7:0] D[7:0] D[7:0] D[7:0] D[7:0] MAD[7:0] A[7:0] MAD3 4.7 K A[15:8] MAD1 4.7 K MAD3 4.7 K LSI53C1000 D[7:0] Q[7:0] MAS0/ HCT374 Q[7:0] D[7:0] HCT374 MAS1/ MAD[2:0] D[2:0] MCE/ HCT377 HCT139 Note: MAD2 pulled LOW internally. MAD bus sense logic enabled for 512 Kbytes of slow memory (150 ns devices, additional time required for HCT139 @ 66 MHz).
Page 365 4-92 (CMP) 4-68, 4-72 (EN64TIBMV) 4-92 (CON) 4-28, 4-47 (ENC[3:0]) 4-32, 4-34 (CP) 5-32 (ENDID[3:0]) 5-20 (CP[7:0]) 4-15 (ENID[3:0]) 4-38 (CSBC) 4-114 (ENNDJ) 4-90 (CSF) 2-51, 4-86 (ENPMJ) 4-89 (CT) 5-31 (EPC) 4-25 LSI53C1000 PCI to Ultra160 SCSI Controller IX-1...
Page 366 (EPER) (MO[5:0]) 4-33 (ERBA[31:11]) 4-14 (MPEE) 4-55 (ERL) 4-63 (MSG) 4-37, 4-39, 4-43 (ERMP) 4-63 (NC) (ESA) 4-112 (NF) 5-35, 5-39 (EWS) 4-32 (NIP[7:0]) 4-18 (FBL[2:0]) 4-55 (O[2:0]) 5-23 (FBL3) 4-55 (OLF) 4-42 (FE) 4-77 (OLF1) 4-44 (FFL[7:0]) 4-51 (OPC) (FLF) 4-53 (OPC[2:0]) 5-14, 5-23,...
Page 367 (SEM) 4-47 Numerics (SFBR) 4-36 (SFS) 4-96, 4-123 2-22 (SGE) 4-69, 4-73 3-18 (SI) 4-49 32/64-bit jump 5-31 (SID[15:0]) 4-13 32-bit addressing (SIEN0) 4-68 3-state (SIEN1) 4-70 64 bit (SIGP) 4-47, 4-52 addressing (SIP) 4-48 addressing in SCRIPTS 2-20 (SIR) 4-40, 4-64 64 Kbytes ROM read cycle 6-60, 6-61...
Page 368 assert test three (CTEST3) 2-9, 2-12, 4-53 SCSI (Cont.) test two (CTEST2) 4-52 MSG/ signal (MSG) 4-37, 4-39 test zero (CTEST0) 4-51 REQ/ signal (REQ) 4-37, 4-39 CHMOV 2-55 RST/ signal (RST) 4-28 class code register SEL/ signal (SEL) 4-37, 4-39 clear DMA FIFO (CLF) 2-51, 4-54...
Page 369 DEVSEL/ checking 2-33 timing (DT[1:0]) checking (EPC) 4-25 DIEN 2-48 error response (EPER) differential mode 2-39 phase mismatch jump (ENPMJ) 4-89 2-51 read direct 5-19 line (ERL) 4-63 disable multiple (ERMP) 4-63 auto FIFO clear (DISFC) 4-90 response to CRC checking 4-115 reselection (RRE) 4-32...
Page 370 GPIO enable (GPIO[4:2]) 4-77 control signals grant parallel ROM 2-59 internal 2-19 SCRIPTS RAM 2-19 interrupt halting 2-51 handshake-to-handshake acknowledge command timer bus activity enable (HTHBA) 4-79 direction timer expired (HTH) 4-71, 4-75 fatal 2-48 timer period (HTH[3:0]) 4-78 halting 2-51 timer scale factor (HTHSF) 4-80...
Page 371 MWE/ 3-14 driver SCSI signals receiver SCSI signals LVDlink 1-2, 1-6, 2-39 benefits new capabilities (NC) operation 2-39 new features in the LSI53C1000 next item pointer register 4-18 Next_Item_Ptr (NIP[7:0]) 4-18 no flush 5-35 M66EN store instruction only 5-39 MAD bus programming...
Page 372 PCI (Cont.) receive rate calculation 2-43 cache line size register received cache mode 2-10 master abort (from master) (RMA) command register target abort (from master) (RTA) commands register configuration info enable (PCICIE) 4-52 address 5-39 configuration register read 6-15, 6-16 address - A[6:0] 5-24 configuration registers...
Page 373 SCRIPTS (Cont.) data compare mask 5-32 block move instructions data compare value 5-33 call instruction 5-28 instruction type 5-27 chained block moves 2-55 interrupt-on-the-fly 5-31 clear instruction 5-16 jump address 5-33 disconnect instruction 5-15 jump if true/false 5-31 jump64 address 5-33 encoded SCSI destination ID 5-20...
Page 374 SCSI (Cont.) interface 2-61 MSG/ signal (MSG) 4-43 SERR/ new phases on the SCSI bus 2-23 SERR/enable (SE) output control latch (SOCL) 4-37 set instruction 5-16 output data latch (SODL) 4-88 SCRIPTS 5-18 parity errors and interrupts 2-35 set/clear parity/CRC error (PAR) 4-70 carry 5-21...
Page 375 synchronous (Cont.) Ultra SCSI SCSI receive 2-39 single-ended transfers 6-65, 6-67 SCSI send 2-38 Ultra160 2-22 transfer rate 2-45 Ultra160 SCSI system benefits application designing an Ultra160 SCSI system 2-22 system error enabling 2-26 system signals LVDlink 2-39 Ultra2 SCSI transfers 6-66, 6-68, 6-69 unexpected disconnect (UDC) 4-70,...
Page 376 IX-12 Index...
Page 377: Customer Feedback
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LSI LSI53C1000 Technical Manual

Chapter 1 Introduction

Chapter 2 Functional Description

Chapter 3 Signal Descriptions

Chapter 4 Registers

Chapter 5 SCSI SCRIPTS Instruction Set

Chapter 6 Speciﬁcations

Appendix A Register Summary

Appendix B External Memory Interface Diagram Examples

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Summary of Contents for LSI LSI53C1000