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LSI LSI53C896 Technical Manual

LSI LSI53C896 Technical Manual

Pci to dual channel ultra2 scsi multifunction controller

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TECHNICAL

MANUAL

LSI53C896

PCI to Dual Channel

*

Ultra2 SCSI

Multifunction Controller

Version 3.2

A p r i l 2 0 0 1

®

Table of Contents

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Page 1 TECHNICAL MANUAL LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller Version 3.2 A p r i l 2 0 0 1 ®...
Page 2 LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties.
Page 3 Preface This book is the primary reference and technical manual for the LSI Logic Corporation LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller. It contains a complete functional description for the product and includes complete physical and electrical speciﬁcations.
Page 4 113 Sylvan Avenue Englewood Cliffs, NJ 07632 (800) 947-7700 Ask for document number ISBN 0-13-796855-8, SCSI: Understanding the Small Computer System Interface LSI Logic World Wide Web Home Page www.lsilogic.com SCSI SCRIPTS™ Processors Programming Guide, Version 2.2, Order Number S14044.A Preface...
Page 5 3/11/98 Changes throughout to reﬂect manual review process and preproduction chip revisions. 1/18/99 Miscellaneous changes/corrections to reﬂect product qualiﬁcation. A table showing LSI53C896 internal pull-up and pull-downs has been added to Chapter 3. 4/12/99 Miscellaneous cosmetic/format changes. 11/99 Final version.
Page 6 Preface...
Page 7: Table Of Contents
Contents Chapter 1 Introduction General Description 1.1.1 New Features in the LSI53C896 Beneﬁts of Ultra2 SCSI Beneﬁts of LVDlink ® TolerANT Technology LSI53C896 Beneﬁts Summary 1.5.1 SCSI Performance 1.5.2 PCI Performance 1.5.3 Integration 1.5.4 Ease of Use 1.5.5 Flexibility 1.5.6 Reliability 1.5.7...
Page 8 Power State D1 2-61 2.5.3 Power State D2 2-61 2.5.4 Power State D3 2-61 Chapter 3 Signal Descriptions Internal Pull-ups on LSI53C896 Signals PCI Bus Interface Signals 3.2.1 System Signals 3.2.2 Address and Data Signals 3.2.3 Interface Control Signals 3.2.4 Arbitration Signals 3.2.5...
Page 9 Power and Ground Signals 3-21 MAD Bus Programming 3-22 Chapter 4 Registers PCI Conﬁguration Registers SCSI Registers 4-19 64-Bit SCRIPTS Selectors 4-107 Phase Mismatch Jump Registers 4-111 Chapter 5 SCSI SCRIPTS Instruction Set SCSI SCRIPTS 5.1.1 Sample Operation Block Move Instructions 5.2.1 First Dword 5.2.2...
Page 10 Typical LSI53C896 Board Application LSI53C896 Block Diagram Parity Checking/Generation 2-30 DMA FIFO Sections 2-31 LSI53C896 Host Interface SCSI Data Paths 2-32 8-Bit HVD Wiring Diagram for Ultra SCSI 2-37 Regulated Termination for Ultra2 SCSI 2-39 Determining the Synchronous Transfer Rate...
Page 11 Block Move Instruction - Third Dword 5-14 First 32-Bit Word of the I/O Instruction 5-15 Second 32-Bit Word of the I/O Instruction 5-22 Read/Write Instruction - First Dword 5-23 Read/Write Instruction - Second Dword 5-24 Transfer Control Instructions - First Dword 5-27 5.10 Transfer Control Instructions - Second Dword...
Page 12 6.38 Target Asynchronous Receive 6-62 6.39 Initiator and Target Synchronous Transfer 6-66 6.40 LSI53C896 329 BGA (Bottom View) 6-70 6.41 LSI53C896 329 BGA Mechanical Drawing 6-71 16 Kbyte Interface with 200 ns Memory 64 Kbyte Interface with 150 ns Memory...
Page 13 System Signals Address and Data Signals Interface Control Signals Arbitration Signals Error Reporting Signals Interrupt Signals 3-10 SCSI Function A GPIO Signals 3-11 SCSI Function B GPIO Signals 3-12 3.10 SCSI Bus Interface Signals 3-13 3.11 SCSI Function A Signals 3-14 3.12 SCSI Function A_SCTRL Signals...
Page 14: Slow Memory (≥ 128 Kbytes) Write Cycle
Output Signals—MAS/[1:0], MCE/, MOE/_TESTOUT, MWE/, TDO Bidirectional Signals—AD[63:0], C_BE[7:0]/, FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR, PAR64, REQ64/, ACK64/ 6.10 Input Signals—CLK, GNT/, IDSEL, INT_DIR, RST/, SCLK, TCK, TDI, TEST_HSC, TEST_RST/, TMS 6.11 Output Signals—INTA, INTB, ALT_INTA, ALT_INTB, REQ/ 6.12 Output Signal—SERR/ 6.13 TolerANT Technology Electrical Characteristics for SE...
Page 15 40.0 Mbytes (16-Bit Transfers) 80 MHz Clock 6-65 6.49 Ultra2 SCSI Transfers 40.0 Mbyte (8-Bit Transfers) or 80.0 Mbyte (16-Bit Transfers) Quadrupled 40 MHz Clock 6-66 6.50 Signal Names and BGA Position 6-68 6.51 Signal Names by BGA Position 6-69 LSI53C896 Register Map Contents...
Page 16 Contents...
Page 17: Introduction
SCSI connectivity and cable length with Low Voltage Differential (LVD) signaling for SCSI devices. The LSI53C896 has a local memory bus for local storage of the device’s BIOS ROM in ﬂash memory or standard EPROMs. The LSI53C896 supports programming of local ﬂash memory for updates to BIOS.
Page 18: Typical Lsi53C896 System Application
It is designed to implement multithreaded I/O algorithms with a minimum of processor intervention, solving the protocol overhead problems of previous intelligent and nonintelligent adapter designs. Figure 1.1 illustrates a typical LSI53C896 system and Figure 1.2 illustrates a typical LSI53C896 board application. Figure 1.1...
Page 19: New Features In The Lsi53C896
PCI Address, Data, Parity and Control Signals 1.1.1 New Features in the LSI53C896 The LSI53C896 is functionally similar to the LSI53C876 PCI to Dual Channel SCSI Multifunction Controller, with added support for Ultra2 SCSI. Some software enhancements, and the use of LVD, are needed to enable the chip to transfer data at Ultra2 SCSI transfer rates.
Page 20: Beneﬁts Of Ultra2 Scsi
SCSI. When enabled, Ultra2 SCSI performs 40 mega transfers per second, which results in approximately double the synchronous transfer rates of Ultra SCSI. The LSI53C896 can perform 16-bit, Ultra2 SCSI synchronous transfers as fast as 80 Mbytes/s on each channel for a total bandwidth of 160 Mbytes/s.
Page 21: Tolerant ® Technology
LVDlink transceivers that can support LVD SCSI, SE, and HVD modes. The LVDlink technology also supports HVD signaling in legacy systems, when external transceivers are connected to the LSI53C896. This allows the LSI53C896 to be used in both legacy and Ultra2 SCSI applications. ®...
Page 22: Lsi53C896 Beneﬁts Summary
TolerANT technology is compatible with both the Alternative One and Alternative Two termination schemes proposed by the American National Standards Institute. 1.5 LSI53C896 Beneﬁts Summary This section provides an overview of the LSI53C896 features and beneﬁts. It contains information on SCSI Performance,...
Page 23: Pci Performance
Performs zero wait-state bus master data bursts up to 264 Mbytes/s (@ 33 MHz). • Supports PCI Cache Line Size register. • Supports PCI Write and Invalidate, Read Line, and Read Multiple commands. • Complies with PCI Bus Power Management Speciﬁcation Revision 1.1. LSI53C896 Beneﬁts Summary...
Page 24: Integration
1.5.3 Integration • Dual channel Ultra2 SCSI PCI Multifunction controller. • Integrated LVD transceivers. • Full 64-bit or 32-bit PCI DMA bus master. • Can be used as a third-party PCI bus DMA controller by using Memory-to-Memory Move instructions. • Integrated SCRIPTS processor.
Page 25: Reliability
Power and ground isolation of I/O pads and internal chip logic. • TolerANT technology provides: – Active negation of SCSI Data, Parity, Request, and Acknowledge signals for improved fast SCSI transfer rates. – Input signal ﬁltering on SCSI receivers improves data integrity, even in noisy cabling environments. LSI53C896 Beneﬁts Summary...
Page 26: Testability
1.5.7 Testability • All SCSI signals accessible through programmed I/O. • SCSI loopback diagnostics. • SCSI bus signal continuity checking. • Support for single step mode operation. • JTAG boundary scan. 1-10 Introduction...
Page 27: Functional Description
The LSI53C896 is composed of the following modules: • 64-bit PCI Interface. • Two independent PCI-to-Wide Ultra2 SCSI Controllers. • ROM/Flash Memory Controller. • Serial EEPROM Controller. Figure 2.1 illustrates the relationship between these modules. LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller...
Page 28: Pci Functional Description
SCSI Bus 2.1 PCI Functional Description The LSI53C896 implements two PCI-to-Wide Ultra2 SCSI controllers in a single package. This conﬁguration presents only one load to the PCI bus and uses one REQ/ - GNT/ pair to arbitrate for PCI bus mastership.
Page 29: Pci Addressing
Function B Conﬁguration register (AD[10:8] = 0b001). At initialization time, each PCI device is assigned a base address (in the case of the LSI53C896, the upper 24 bits of the address are selected) for memory accesses and I/O accesses. On every access, the LSI53C896 compares its assigned base addresses with the value on the Address/Data bus during the PCI address phase.
Page 30: Pci Bus Commands And Functions Supported
2.1.1.3 Memory Space The PCI speciﬁcation deﬁnes memory space as a contiguous 64-bit memory address that is shared by all system resources, including the LSI53C896. Base Address Register One (MEMORY) determines which 1 Kbyte memory area this device occupies. Each SCSI function uses a 8 Kbyte SCRIPTS RAM memory space.Base Address Register Two...
Page 31: Pci Bus Commands And Encoding Types For The Lsi53C896
Chip Test Three (CTEST3) register. 2.1.2.1 Interrupt Acknowledge Command The LSI53C896 does not respond to this command as a slave and it never generates this command as a master. 2.1.2.2 Special Cycle Command The LSI53C896 does not respond to this command as a slave and it never generates this command as a master.
Page 32 When decoding I/O cycles, the LSI53C896 decodes the lower 32 address bits and ignores the upper 32 address bits. 2.1.2.5 Reserved Command The LSI53C896 does not respond to this command as a slave and it never generates this command as a master. 2.1.2.6 Memory Read Command The Memory Read command reads data from an agent mapped in the Memory Address Space.
Page 33 This command is identical to the Memory Read command except that it additionally indicates that the master may intend to fetch more than one cache line before disconnecting. The LSI53C896 supports PCI Memory Read Multiple functionality and issues Memory Read Multiple commands on the PCI bus when the Read Multiple mode is enabled.
Page 34 The Read Line function in the LSI53C896 takes advantage of the PCI 2.1 speciﬁcation regarding issuing of this command.
Page 35 • The chip is aligned to a cache line boundary. When these conditions are met, the LSI53C896 issues a Write and Invalidate command instead of a Memory Write command during all PCI write cycles. PCI Functional Description...
Page 36 Latency – In accordance with the PCI speciﬁcation, the latency timer is ignored when issuing a Memory Write and Invalidate command such that when a latency time-out occurs, the LSI53C896 continues to transfer up to a cache line boundary. At that point, the chip relinquishes the bus, and ﬁnishes the transfer at a later time using another bus ownership.
Page 37: Internal Arbiter
PCI bus access. There are two independent bus mastering functions inside the LSI53C896, one for each of the SCSI functions. The internal arbiter uses a round robin arbitration scheme to decide which internal bus mastering function may arbitrate for access to the PCI bus.
Page 38 • The programmed burst size (in Dwords) must be equal to or greater than the cache line size register. The DMA Mode (DMODE) register bits [7:6] and the Chip Test Five (CTEST5) register bit 2 are the burst length bits. •...
Page 39 2.1.4.3 Memory Read Caching Which type of Memory Read command gets issued depends on the starting location of the transfer and the number of bytes to be transferred. During reads, no cache alignment is done (this is not required nor optimal per PCI 2.1 speciﬁcation) and reads will always be either a programmed burst length in size, as set in the DMA Mode (DMODE)
Page 40 Table 2.2 PCI Cache Mode Alignment Host Memory 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 2-14 Functional Description...
Page 41 2.1.4.5 Examples: The examples in this section employ the following abbreviations: MR = Memory Read, MRL = Memory Read Line, MRM = Memory Read Multiple, MW = Memory Write, MWI = Memory Write and Invalidate. Read Example 1 – Burst = 4 Dwords, Cache Line Size = 4 Dwords: A to B: MRL (6 bytes) A to C:...
Page 42 Read Example 2 – Burst = 8 Dwords, Cache Line Size = 4 Dwords: A to B: MRL (6 bytes) A to C: MRL (13 bytes) A to D: MRM (17 bytes) C to D: MRM (5 bytes) C to E: MRM (21 bytes) D to F: MRM (31 bytes)
Page 43 Write Example 1 – Burst = 4 Dwords, Cache Line Size = 4 Dwords: A to B: MW (6 bytes) A to C: MW (13 bytes) A to D: MW (17 bytes) C to D: MW (5 bytes) C to E: MW (3 bytes) MWI (16 bytes) MW (2 bytes)
Page 44 Write Example 2 – Burst = 8 Dwords, Cache Line Size = 4 Dwords: A to B: MW (6 bytes) A to C: MW (13 bytes) A to D: MW (17 bytes) C to D: MW (5 bytes) C to E: MW (3 bytes) MWI (16 bytes) MW (2 bytes)
Page 45: Scsi Functional Description
Invalidate commands are issued. The LSI53C896 is little endian only. 2.2 SCSI Functional Description The LSI53C896 provides two Ultra2 SCSI controllers on a single chip. Each Ultra2 SCSI controller provides a SCSI function that supports an 8-bit or 16-bit bus. Each controller supports Wide Ultra2 SCSI synchronous transfer rates up to 80 Mbytes/s on a LVD SCSI bus.
Page 46: Scripts Processor
The LSI53C896 offers low level register access or a high-level control interface. Like ﬁrst generation SCSI devices, the LSI53C896 is accessed as a register-oriented device. The ability to sample and/or assert any signal on the SCSI bus is used in error recovery and diagnostic procedures.
Page 47: Internal Scripts Ram
SCRIPTS instructions. 2.2.2 Internal SCRIPTS RAM The LSI53C896 has 8 Kbytes (2048 x 32 bits) of internal, general purpose RAM for each SCSI function. The RAM is designed for SCRIPTS program storage, but is not limited to this type of information.
Page 48: 64-Bit Addressing In Scripts
4 Gbyte boundary. 2.2.4 Hardware Control of SCSI Activity LED The LSI53C896 has the ability to control a LED through the GPIO_0 pin to indicate that it is connected to the SCSI bus. Formerly this function was done by a software driver.
Page 49: Designing An Ultra2 Scsi System
The CON (Connected) bit in Interrupt Status Zero (ISTAT0) will be set anytime the LSI53C896 is connected to the SCSI bus either as an initiator or a target. This will happen after the LSI53C896 has successfully completed a selection or when it has successfully responded to a selection or reselection.
Page 50: Prefetching Scripts Instructions
SCRIPTS RAM, prefetching is not necessary when fetching instructions from this memory. The LSI53C896 may ﬂush the contents of the prefetch unit under certain conditions to ensure that the chip always operates from the most current version of the SCRIPTS instruction. When one of these conditions applies, the contents of the prefetch unit are automatically ﬂushed.
Page 51: Opcode Fetch Burst Capability
Setting the Burst Opcode Fetch Enable bit (bit 1) in the DMA Mode (DMODE) register (0x38) causes the LSI53C896 to burst in the ﬁrst two Dwords of all instruction fetches. If the instruction is a Memory-to- Memory Move, the third Dword is accessed in a separate ownership. If the instruction is an Indirect Type, the additional Dword is accessed in a subsequent bus ownership.
Page 52: Load/Store Instructions
CLAMP, HIGH-Z, and IDCODE instructions. The LSI53C896 uses an 8-bit instruction register to support all boundary scan instructions. The data registers included in the device are the Boundary Data register, the IDCODE register, and the Bypass register.
Page 53: Scsi Loopback Mode
SCSI Test Two (STEST2) register, bit 4, the LSI53C896 allows control of all SCSI signals whether the chip is operating in the initiator or target mode. For more information on this mode of operation refer to the LSI Logic SCSI SCRIPTS Processors Programming Guide.
Page 54: Bits Used For Parity Control And Generation
Enable (CTEST4), Bit 3 phases. Master Data Parity Error DMA Status Set when the LSI53C896, as a PCI master, detects a (DSTAT), Bit 6 target device signaling a parity error during a data phase. Master Data Parity Error DMA Interrupt...
Page 55: Scsi Parity Errors And Interrupts
Table 2.4 SCSI Parity Control ASEP Description Does not check for parity errors. Parity is generated when sending SCSI data. Asserts odd parity when sending SCSI data. Does not check for parity errors. Parity is generated when sending SCSI data. Asserts even parity when sending SCSI data.
Page 56: Dma Fifo
Figure 2.2 Parity Checking/Generation Asynchronous Synchronous Synchronous Asynchronous SCSI Send SCSI Send SCSI Receive SCSI Receive PCI Interface** PCI Interface** PCI Interface** PCI Interface** DMA FIFO* DMA FIFO* DMA FIFO* DMA FIFO* (64 Bits x 118) (64 Bits x 118) (64 Bits x 118) (64 Bits x 118) SCSI FIFO*...
Page 57 2, 4, 8, 16, 32, 64, or 128 Dword bursts across the PCI bus interface. 2.2.12.1 Data Paths The data path through the LSI53C896 is dependent on whether data is being moved into or out of the chip, and whether SCSI data is being transferred asynchronously or synchronously.
Page 58: Lsi53C896 Host Interface Scsi Data Paths
Figure 2.4 LSI53C896 Host Interface SCSI Data Paths Asynchronous Synchronous Synchronous Asynchronous SCSI Send SCSI Send SCSI Receive SCSI Receive PCI Interface PCI Interface PCI Interface PCI Interface DMA FIFO DMA FIFO DMA FIFO DMA FIFO (8 Bytes x 118)
Page 59 SSTAT0 or SSTAT2 register, then the least signiﬁcant byte or the most signiﬁcant byte in the SODL register is full. Checking this bit also reveals bytes left in the SODL register from a Chained Move operation with an odd byte count. Synchronous SCSI Send –...
Page 60 left in the DMA FIFO. To make this calculation, subtract the seven least signiﬁcant bits of the DBC register from the 7-bit value of the DMA FIFO (DFIFO) register. AND the result with 0x7F for a byte count between zero and 112. If the DMA FIFO size is set to 944 bytes (bit 5 of the Chip Test Five (CTEST5)
Page 61: Scsi Bus Interface
The LSI Logic LVDlink transceivers operate in LVD or SE modes. They allow the chip to detect a HVD signal when the chip is connected to external HVD transceivers. The LSI53C896 automatically detects which type of signal is connected, based on the voltage detected by the DIFFSENS pin.
Page 62: Hvd Signals
SMSG−, SC_D−, SI_O− and SREQ−. DIFFSENS Input to the LSI53C896 used to detect the voltage level of a SCSI signal to determine whether it is a SE, LVD, or HVD signal. The encoded result is displayed in SCSI Test Four (STEST4) bits 7 and 6.
Page 63: 8-Bit Hvd Wiring Diagram For Ultra Scsi
Figure 2.5 8-Bit HVD Wiring Diagram for Ultra SCSI Schottky DIFFSENS Diode DIFFSENS (pin 21) LSI53C8XX 1.5 K SN75976A2 −SEL (42) CDE0 SEL+ 1.5 K (41) +SEL CDE1 1B− BSY+ −BSY (34) CDE2 RST+ +BSY (33) 2B− −RST (38) SEL− (37) +RST 1.5 K...
Page 64 To interface the LSI53C896 to the SN75976A, connect the positive pins in the SCSI LVD pair of the LSI53C896 directly to the transceiver enables (DE/RE/). These signals control the direction of the channels on the SN75976A. − − −, The SCSI bidirectional control and data pins (SD[7:0]...
Page 65 For information on terminators that support LVD, refer to the SPI-2 draft standard. Note: If the LSI53C896 is to be used in a design with only an 8-bit SCSI bus, all 16 data lines must be terminated. Figure 2.6 Regulated Termination for Ultra2 SCSI UCC5630 −...
Page 66: Select/Reselect During Selection/Reselection
(SCSI Chip ID (SCID) bits 5 and 6, respectively) should both be asserted so that the LSI53C896 may respond as an initiator or as a target. If only selection is enabled, the LSI53C896 cannot be reselected as an initiator. There are also status and interrupt bits in the...
Page 67: Determining The Synchronous Transfer Rate
2.2.15.1 Determining the Data Transfer Rate Synchronous data transfer rates are controlled by bits in two different registers of the LSI53C896. Following is a brief description of the bits. Figure 2.7 illustrates the clock division factors used in each register, and the role of the register bits in determining the transfer rate.
Page 68 25 ns, which is half the 50 ns period allowed under Ultra SCSI. This will allow a maximum transfer rate of 80 Mbytes/s on a 16-bit, LVD SCSI bus. The LSI53C896 has a SCSI clock quadrupler that must be enabled for the chip to perform Ultra2 SCSI transfers with a 40 MHz oscillator.
Page 69: Interrupt Handling
INTB/, but can be routed to INTA/ if a pull-up is connected to MAD[4]. See Section 3.7, “MAD Bus Programming,” additional information. 2.2.16.2 Registers The registers in the LSI53C896 that are used for detecting or deﬁning interrupts are ISTAT, SCSI Interrupt Status Zero (SIST0), SCSI Interrupt...
Page 70 Reading these registers determines which condition or conditions caused the SCSI-type interrupt, and clears that SCSI interrupt condition. If the LSI53C896 is receiving data from the SCSI bus and a fatal interrupt condition occurs, the chip attempts to send the contents of the DMA FIFO to memory before generating the interrupt.
Page 71 DSTAT – The DMA Status (DSTAT) register contains the DMA-type interrupt bits. Reading this register determines which condition or conditions caused the DMA-type interrupt, and clears that DMA interrupt condition. Bit 7 in DSTAT, DFE, is purely a status bit; it will not generate an interrupt under any circumstances and will not be cleared when read.
Page 72 When the LSI53C896 is operating in the Initiator mode, only the Function Complete (CMP), Selected (SEL), Reselected (RSL), General Purpose Timer Expired (GEN), and Handshake-to-Handshake Timer Expired (HTH) interrupts are nonfatal. When operating in the Target mode, CMP, SEL, RSL, Target mode: SATN/ active (M/A), GEN, and HTH are nonfatal.
Page 73 Masking an interrupt after INTA/ (or INTB/) is asserted does not cause deassertion of INTA/ (or INTB/). 2.2.16.5 Stacked Interrupts The LSI53C896 will stack interrupts, if they occur, one after the other. If the SIP or DIP bits in the Interrupt Status Zero (ISTAT0) register are set (ﬁrst level), then there is already at least one pending interrupt, and any...
Page 74 These ‘locked out’ SCSI interrupts are posted as soon as the DMA FIFO is empty. 2.2.16.6 Halting in an Orderly Fashion When an interrupt occurs, the LSI53C896 attempts to halt in an orderly fashion. • If the interrupt occurs in the middle of an instruction fetch, the fetch is completed, except in the case of a Bus Fault.
Page 75 2.2.16.7 Sample Interrupt Service Routine The following is a sample of an interrupt service routine for the LSI53C896. It can be repeated if polling is used, or should be called when the INTA/ (or INTB/) pin is asserted if hardware interrupts are used.
Page 76: Interrupt Routing
This should cause the system to re-enter the interrupt service routine. 2.2.17 Interrupt Routing This section documents the recommended approach to RAID ready interrupt routing for the LSI53C896. In order to be compatible with AMI RAID upgrade products and the LSI53C896, the following requirements must be met: •...
Page 77: Interrupt Routing Hardware Using The Lsi53C896
The ﬁrst option is to have the SCSI core load its PCI Subsystem ID using a serial EPROM on power-up. If bit 15 in this ID is set, the LSI Logic BIOS and operating system drivers will ignore the chip. This makes it possible to control the assignment of the mainboard SCSI cores using a conﬁguration utility.
Page 78: Chained Block Moves
The second option is to provide mainboard and system BIOS support for NVS. The SCSI core may then be enabled or disabled using the SCSI BIOS conﬁguration utility. Not all versions of the LSI Logic drivers support this capability. The third option is to have the system BIOS not report the existence of the SCSI controller chips when the SCSI BIOS and operating systems make PCI BIOS calls.
Page 79: Block Move And Chained Block Move Instructions
Figure 2.9 Block Move and Chained Block Move Instructions Host Memory SCSI Bus 0x03 0x02 0x01 0x00 0x04 0x03 0x07 0x06 0x05 0x04 0x06 0x05 0x0B 0x0A 0x09 0x08 0x0F 0x0E 0x0D 0x0C 0x13 0x12 0x11 0x10 0x09 0x07 0x0B 0x0A 0x0D 0x0C 32 Bits 16 Bits...
Page 80 transfer, the ﬁrst byte (the high-order byte) of the next data send transfer is “married” with the stored low-order byte in the SODL register; and the two bytes are sent out across the bus, regardless of the type of Block Move instruction (normal or chained).
Page 81 2.2.18.5 Chained Block Move SCRIPTS Instruction A chained Block Move SCRIPTS instruction is primarily used to transfer consecutive data send or data receive blocks. Using the chained Block Move instruction facilitates partial receive transfers and allows correct partial send behavior without additional opcode overhead. Behavior of the chained Block Move instruction varies slightly for sending and receiving data.
Page 82: Parallel Rom Interface
Block Moves. 2.3 Parallel ROM Interface The LSI53C896 supports up to one megabyte of external memory in binary increments from 16 Kbytes to allow the use of expansion ROM for add-in PCI cards. Both functions of the device share the ROM interface.
Page 83: Parallel Rom Support
MAD[3:1] should be pulled HIGH. Note: There are internal pull-downs on all of the MAD bus signals. The LSI53C896 allows the system to determine the size of the available external memory using the Expansion ROM Base Address register in the PCI conﬁguration space.
Page 84: Serial Eeprom Interface
2.4 Serial EEPROM Interface The LSI53C896 implements an interface that allows attachment of a serial EEPROM device to the GPIO0 and GPIO1 pins for each SCSI function. There are two modes of operation relating to the serial EEPROM and the...
Page 85: No Download Mode
PCI speciﬁcation, with a default value of 0x1000 and 0x1000 respectively. 2.5 Power Management The LSI53C896 complies with the PCI Bus Power Management Interface Speciﬁcation, Revision 1.1. The PCI Function Power States D0, D1, D2, and D3 are deﬁned in that speciﬁcation.
Page 86: Power State D0
Power state actions are separate for each function. 2.5.1 Power State D0 Power state D0 is the maximum power state and is the power-up default state for each function. The LSI53C896 is fully functional in this state. 2-60 Functional Description...
Page 87: Power State D1
Power state D1 is a lower power state than D0. A function in this state places the LSI53C896 core in the snooze mode and disables the SCSI CLK. In the snooze mode, a SCSI reset does not generate an IRQ/ signal.
Page 88 2-62 Functional Description...
Page 89: Signal Descriptions
Chapter 3 Signal Descriptions This chapter presents the LSI53C896 pin conﬁguration and signal deﬁnitions using tables and illustrations. Figure 3.1 is the functional signal grouping. The signal descriptions begin with Table 3.2. The signal descriptions are organized into functional groups: •...
Page 90: Lsi53C896 Functional Signal Grouping
Figure 3.1 LSI53C896 Functional Signal Grouping LSI53C896 SCLK System RST/ AD[63:0] Address A_SD[15:0]/ C_BE[7:0] A_SDP[1:0]/ Data A_DIFFSENS PAR64 ACK64/ A_SC_D/ REQ64/ A_SI_O/ SCSI FRAME/ A_SMSG/ Function Interface TRDY/ A_SREQ/ Control IRDY/ A_SREQ2/ STOP/ A_SACK/ A_SCTRL/ DEVSEL/ A_SACK2/ IDSEL A_SBSY/ A_SATN/...
Page 91 There are ﬁve signal type deﬁnitions: Input, a standard input-only signal. Output, a standard output driver (typically a Totem Pole Output). Input and output (bidirectional). 3-state, a bidirectional, 3-state input/output signal. S/T/S Sustained 3-state, an active LOW 3-state signal owned and driven by one and only one agent at a time.
Page 92: Internal Pull-Ups On Lsi53C896 Signals
3.1 Internal Pull-ups on LSI53C896 Signals Several LSI53C896 signals use internal pull-ups and pull-downs. Table 3.1 describes the conditions that enable these pull-ups and pull-downs. Table 3.1 LSI53C896 Internal Pull-ups and Pull-downs Pull-up Pin Name current Conditions for Pull-up 25 µA INTA/, INTB/, ALT_INTA/, Pull-up enabled when the “AND-tree”...
Page 93: Pci Bus Interface Signals
3.2 PCI Bus Interface Signals The PCI Bus Interface Signals section contains tables describing the signals for the following signal groups: System Signals, Address and Data Signals, Interface Control Signals, Arbitration Signals, Error Reporting Signals, Interrupt Signals, SCSI Function A GPIO Signals, and SCSI Function B GPIO Signals.
Page 94: Address And Data Signals
3.2.2 Address and Data Signals Table 3.3 describes the signals for the Address and Data Signals group. Table 3.3 Address and Data Signals Name Bump Type Strength Description AD[63:0] Y5, AB5, AC5, AA6, 16 mA Physical Dword Address and Data are Y6, AB6, AC6, AA7, multiplexed on the same PCI pins.
Page 95: Interface Control Signals
Table 3.3 Address and Data Signals (Cont.) Name Bump Type Strength Description PAR64 16 mA Parity64 is the even parity bit that protects the AD[63:32] and C_BE[7:4]/ lines. During address phase, both the address and command bits are covered. During data phase, both data and byte enables are covered.
Page 96: Arbitration Signals
Table 3.4 Interface Control Signals (Cont.) Name Bump Type Strength Description STOP/ S/T/S 16 mA Stop indicates that the selected target is requesting the master to stop the current transaction. DEVSEL/ S/T/S 16 mA Device Select indicates that the driving device has decoded its address as the target of the current access.
Page 97: Error Reporting Signals
3.2.5 Error Reporting Signals Table 3.6 describes the signals for the Error Reporting Signals group. Table 3.6 Error Reporting Signals Name Bump Type Strength Description PERR/ S/T/S 16 mA Parity Error may be pulsed active by an agent that detects a data parity error.
Page 98: Interrupt Signals
INTA/ at power-up using the INTA/ enable sense resistor (pull-up on MAD[4]). This causes the LSI53C896 to program the SCSI Function B PCI Interrupt Pin register (0x3D) to 0x01. This interrupt pin is disabled if INT_DIR is driven LOW.
Page 99: Scsi Function A Gpio Signals
MAD[7] pin to serve as the clock signal for the serial EEPROM interface. When General Purpose Pin Control (GPCNTL) bit 7 is set, this pin drives LOW when the LSI53C896 is bus master. A_GPIO2 AA16 8 mA SCSI Function A General Purpose I/O pin 2.
Page 100: Scsi Function B Gpio Signals
EEPROM interface. When General Purpose Pin Control (GPCNTL) bit 7 is set, this pin is driven LOW when the LSI53C896 is bus master. B_GPIO2 AB15 8 mA SCSI Function B General Purpose I/O pin 2. This pin powers up as an input.
Page 101: Scsi Bus Interface Signals
3.3 SCSI Bus Interface Signals The SCSI Bus Interface Signals section contains tables describing the signals for the following signal groups: SCSI Bus Interface Signals, SCSI Function A Signals, and SCSI Function B Signals. SCSI Function A signals and SCSI Function B signals each have a subgroup: SCSI Function A_SCTRL Signals signals and...
Page 102 Table 3.11 describes the signals for the SCSI Function A Signals group. Table 3.11 SCSI Function A Signals Name Bump Type Strength Description A_SD[15:0]− B5, C5, B4, C4, 48 mA SCSI Function A Data and Parity. D19, A19, D18, SCSI LVD Mode: Negative half of LVDlink pair for A18, D11, A9, D9, SCSI data and parity lines.
Page 103 3.3.1.1 A_SCTRL Signals Table 3.12 describes the SCSI Function A_SCTRL Signals group. Table 3.12 SCSI Function A_SCTRL Signals Name Bump Type Strength Description SCSI Function A Control includes the following signals: A_SC_D− 48 mA SCSI phase line, command/data. A_SC_D+ SCSI A_SI_O−...
Page 104: Scsi Function B Signals
3.3.2 SCSI Function B Signals This section describes the signals for the SCSI Function B Signals group. It is divided into two tables: SCSI Function B Signals SCSI Function B_SCRTL Signals. Table 3.13 describes the SCSI Function B Signals group. Table 3.13 SCSI Function B Signals Name...
Page 105 Table 3.13 SCSI Function B Signals (Cont.) Name Bump Type Strength Description B_DIFFSENS SCSI Function B Differential Sense pin detects the present mode of the SCSI bus when connected to the DIFFSENS signal on the physical SCSI bus. LVD Mode: When a voltage between 0.7 V and 1.9 V is present on this pin, the SCSI Function B will operate in the LVD mode.
Page 106 Table 3.14 describes the SCSI Function B_SCRTL Signals group. Table 3.14 SCSI Function B_SCRTL Signals Name Bump Type Strength Description SCSI Function B Control includes the following signals: B_SC_D− 48 mA SCSI phase line, command/data. B_SD_D+ SCSI B_SI_O− SCSI phase line, input/output. B_SI_O+ B_SMSG−...
Page 107: Flash Rom And Memory Interface Signals
EPROM or ﬂash memory during read operations. It is also used to test the connectivity of the LSI53C896 signals in the “AND-tree” test mode. The MOE/_TESTOUT pin is only driven as the test out function when the ZMODE bit...
Page 108: Test Interface Signals
EPROM or ﬂash memory during read operations. It is also used to test the connectivity of the LSI53C896 signals in the “AND- tree” test mode. The MOE/_TESTOUT pin is only driven as the test out function when the ZMODE bit (Chip Control 1 (CCNTL1), bit 7) is set.
Page 109: Power And Ground Signals
3.6 Power and Ground Signals Table 3.17 describes the signals for the Power and Ground Signals group. Table 3.17 Power and Ground Signals Name Bump Type Strength Description D4, D12, D20, M4, M10– Ground for PCI bus drivers/receivers, SCSI 14, M20, AA3, AA21, bus drivers/receivers, local memory K10–14, L10–14, C3, interface drivers, and other I/O pins.
Page 110: Mad Bus Programming
3.7 MAD Bus Programming The MAD[7:0] pins, in addition to serving as the address/data bus for the local memory interface, also are used to program power-up options for the chip. A particular option is programmed allowing the internal pull-down current sink to pull the pin LOW at reset or by connecting a 4.7 kΩ...
Page 111 • MAD[3:1] – These pins set the size of the external expansion ROM device attached. Encoding for these pins is listed in Table 3.18 (“0” indicates a pull-down resistor is attached, “1” indicates a pull-up resistor attached). Table 3.18 Decode of MAD[3:1] Pins MAD[3:1] Available Memory Space 16 Kbytes...
Page 112 3-24 Signal Descriptions...
Page 113: Pci Conﬁguration Registers
Chapter 4 Registers This section contains descriptions of all LSI53C896 registers. The term “set” is used to refer to bits that are programmed to a binary one. Similarly, the term “cleared” is used to refer to bits that are programmed to a binary zero.
Page 114 Support of other PCI-compliant registers is optional. In the LSI53C896, registers that are not supported are not writable and return all zeros when read. Only those registers and bits that are currently supported by the LSI53C896 are described in this chapter. Note: Reserved bits should not be accessed.
Page 115 Command register provides coarse control over a device’s ability to generate and respond to PCI cycles. When a zero is written to this register, the LSI53C896 is logically disconnected from the PCI bus for all accesses except conﬁguration accesses. Reserved...
Page 116 Reserved Enable Bus Mastering This bit controls the ability of the LSI53C896 to act as a master on the PCI bus. A value of zero disables this device from generating PCI bus master accesses. A value of one allows the LSI53C896 to behave as a bus master.
Page 117 15 and not affect any other bits, write the value 0x8000 to the register. Detected Parity Error (from Slave) This bit is set by the LSI53C896 whenever it detects a data parity error, even if data parity error handling is disabled.
Page 118 These bits are read only and should indicate the slowest time that a device asserts DEVSEL/ for any bus command except Conﬁguration Read and Conﬁguration Write. The LSI53C896 supports a value of 0b01. Data Parity Error Reported This bit is set when the following conditions are met: •...
Page 119 Registers: 0x09–0x0B Class Code Read Only Class Code [23:0] This 24-bit register is used to identify the generic function of the device. The upper byte of this register is a base class code, the middle byte is a subclass code, and the lower byte identiﬁes a speciﬁc register-level programming interface.
Page 120 This 8-bit register identiﬁes the layout of bytes 0x10 through 0x3F in conﬁguration space and also whether or not the device contains multiple functions. Since the LSI53C896 is a multifunction controller the value of this register is 0x80. Register: 0x0F...
Page 121 [31:0] This base address register is used to map the operating register set into I/O space. The LSI53C896 requires 256 bytes of I/O space for this base address register. It has bit zero hardwired to one. Bit 1 is reserved and returns a zero on all reads, and the other bits are used to map the device into I/O space.
Page 122 This base register is used to map the SCRIPTS RAM into memory space. The default value of this register is 0x0000000000000004. The LSI53C896 requires 8192 bytes of address space for this base register. This register has bits [12:0] hardwired to 0b0000000000100.
Page 123 Registers: 0x2C–0x2D Subsystem Vendor ID Read Only SVID If MAD[7] Is HIGH If MAD[7] is LOW SVID Subsystem Vendor ID [15:0] This 16-bit register is used to uniquely identify the vendor manufacturing the add-in board or subsystem where this PCI device resides. It provides a mechanism for an add-in card vendor to distinguish its cards from another vendor’s cards, even if the cards have the same PCI controller installed on them (and therefore the same...
Page 124 Registers: 0x2E–0x2F Subsystem ID Read Only If MAD[7] Is HIGH If MAD[7] is LOW Subsystem ID [15:0] This 16-bit register is used to uniquely identify the add-in board or subsystem where this PCI device resides. It provides a mechanism for an add-in card vendor to distinguish its cards from one another even if the cards have the same PCI controller installed on them (and therefore the same Vendor ID and Device ID).
Page 125 Expansion ROM Base Address register with all ones and then reading back the register. The SCSI functions of the LSI53C896 respond with zeros in all don’t care locations. The ones in the remaining bits represent the binary version of the external memory size.
Page 126 Register: 0x3C Interrupt Line Read/Write Interrupt Line [7:0] This register is used to communicate interrupt line routing information. POST software writes the routing information into this register as it conﬁgures the system. The value in this register tells which input of the system interrupt controller(s) the device’s interrupt pin is connected to.
Page 127 Max_Lat is used to specify how often the device needs to gain access to the PCI bus. The value speciﬁed in these registers is in units of 0.25 microseconds. The LSI53C896 SCSI function sets this register to 0x40. PCI Conﬁguration Registers...
Page 128 AUXC PMEC VER[2:0] PMES PME_Support [15:11] Bits [15:11] deﬁne the power management states in which the LSI53C896 will assert the PME pin. These bits are all set to zero because the LSI53C896 does not provide a PME signal. 4-16 Registers...
Page 129 D2_Support The LSI53C896 sets this bit to indicate support for power management state D2. D1_Support The LSI53C896 sets this bit to indicate support for power management state D1. AUXC Aux_Current [8:6] The LSI53C896 always returns zeros. This feature is not supported.
Page 130 DSLT[3:0] Data_Select [12:9] The LSI53C896 does not support the data register. Therefore, these four bits are always cleared. PME_Enable The LSI53C896 always returns zero for this bit to indicate that PME assertion is disabled. Reserved [7:2] PWS[1:0] Power State [1:0] Bits [1:0] are used to determine the current power state of the LSI53C896.
Page 131: Scsi Registers
The address map of the SCSI registers is shown in Table 4.2. Note: The only registers that the host CPU can access while the LSI53C896 is executing SCRIPTS are the Interrupt Status Zero (ISTAT0), Interrupt Status One...
Page 132 Table 4.2 SCSI Register Map 16 15 SCNTL3 SCNTL2 SCNTL1 SCNTL0 0x00 GPREG SDID SXFER SCID 0x04 SBCL SSID SOCL SFBR 0x08 SSTAT2 SSTAT1 SSTAT0 DSTAT 0x0C 0x10 MBOX1 MBOX0 ISTAT1 ISTAT0 0x14 CTEST3 CTEST2 CTEST1 CTEST0 0x18 TEMP 0x1C CTEST6 CTEST5 CTEST4...
Page 133 Simple arbitration Reserved Reserved Full arbitration, selection/reselection Simple Arbitration The LSI53C896 SCSI function waits for a bus free condition to occur. It asserts SBSY/ and its SCSI ID (contained in the SCSI Chip ID (SCID) register) onto the SCSI bus. If...
Page 134 2. START Start Sequence When this bit is set, the LSI53C896 starts the arbitration sequence indicated by the Arbitration Mode bits. The Start Sequence bit is accessed directly in low level mode. During SCSI SCRIPTS operations, this bit is controlled by the SCRIPTS processor.
Page 135 WATN Select with SATN/ on a Start Sequence When this bit is set and the LSI53C896 SCSI function is in the initiator mode, the SATN/ signal is asserted during selection of a SCSI target device. This is to inform the target that the LSI53C896 SCSI function has a message to send.
Page 136 This is done using the SCRIPTS language (SET TARGET or CLEAR TARGET). When this bit is set, the chip is a target device by default. When this bit is cleared, the LSI53C896 SCSI function is an initiator device by default. Caution:...
Page 137 This bit is automatically set any time the LSI53C896 SCSI function is connected to the SCSI bus as an initiator or as a target. It is set after the LSI53C896 SCSI function successfully completes arbitration or when it has responded to a bus initiated selection or reselection. This bit is also set after the chip wins simple arbitration when operating in low level mode.
Page 138 Arbitration is retried until won. At that point, the LSI53C896 SCSI function holds SBSY and SSEL asserted, and waits for a select or reselect sequence. The Immediate Arbitration bit is cleared automatically when the selection or reselection sequence is completed, or times out.
Page 139 written to the I/O bit in SCSI Output Control Latch (SOCL). This bit is self-clearing. Do not set it for low level operation. Caution: Writing to this register while not connected may cause the loss of a selection/reselection by clearing the Connected bit.
Page 140 LSI53C896 SCSI function stores the last byte in the SCSI Wide Residue (SWIDE) register during a receive operation, or in the SCSI Output Data Latch (SODL) register during a send operation. This byte is combined with the ﬁrst byte from the subsequent transfer so that a wide transfer is completed.
Page 141 Ultra SCSI Enable Setting this bit enables Ultra SCSI or Ultra2 SCSI synchronous transfers. The default value of this bit is 0. This bit should remain cleared if the LSI53C896 is not operating in Ultra SCSI mode or faster. SCSI Registers...
Page 142 When this bit is set, the signal ﬁltering period for SREQ/ and SACK/ automatically changes to 8 ns for Ultra2 SCSI or 15 ns for Ultra SCSI, regardless of the value of the Extend REQ/ACK Filtering bit in the SCSI Test Two (STEST2) register.
Page 143 Enable Response to Selection When this bit is set, the LSI53C896 SCSI function is able to respond to bus-initiated selection at the chip ID in the Response ID Zero (RESPID0)
Page 144 ENC[3:0] Encoded Chip SCSI ID [3:0] These bits are used to store the LSI53C896 SCSI function encoded SCSI ID. This is the ID which the chip asserts when arbitrating for the SCSI bus. The IDs that the LSI53C896 SCSI function responds to when selected or reselected are conﬁgured in the...
Page 145 (This SCSI synchronous core clock is determined in SCNTL3 bits [6:4], ExtCC = 1 if SCNTL1 bit 7 is asserted and the LSI53C896 is sending data. ExtCC = 0 if the LSI53C896 is receiving data.) SXFERP = 100 ÷ 25 = 4...
Page 146 Table 4.3 shows examples of synchronous transfer periods and rates for SCSI-1. Table 4.3 Examples of Synchronous Transfer Periods and Rates for SCSI-1 Synch. SCSI CLK Synch. Transfer ÷ SCNTL3 Transfer Rate CLK (MHz) Bits [6:4] XFERP Period (ns) (Mbytes) 66.67 5.55 66.67...
Page 147 Table 4.5 describes the possible combinations and their relationship to the synchronous data offset used by the LSI53C896 SCSI function. These bits determine the LSI53C896 SCSI function’s method of transfer for Data-In and Data-Out phases only. All other information transfers occur asynchronously.
Page 148 Table 4.5 Maximum Synchronous Offset Synchronous Offset 0-Asynchronous 4-36 Registers...
Page 149 Register: 0x06 SCSI Destination ID (SDID) Read/Write ENC[3:0] Reserved [7:4] ENC[3:0] Encoded Destination SCSI ID [3:0] Writing these bits sets the SCSI ID of the intended initiator or target during SCSI reselection or selection phases, respectively. When executing SCRIPTS, the SCRIPTS processor writes the destination SCSI ID to this register.
Page 150 Memory Move. However, it can be loaded using SCRIPTS Read/Write operations. To load the SFBR with a byte stored in system memory, the byte must ﬁrst be moved to an intermediate LSI53C896 SCSI function register (such as the SCRATCH register), and then to the SFBR. 4-38...
Page 151 SCSI Output Control Latch (SOCL) is used only when transferring data using programmed I/O. Some bits are set or cleared when executing SCSI SCRIPTS. Do not write to the register once the LSI53C896 SCSI function starts executing normal SCSI SCRIPTS. SCSI Registers 4-39...
Page 152 Reading the SCSI Selector ID (SSID) register immediately after the LSI53C896 SCSI function is selected or reselected returns the binary-encoded SCSI ID of the device that performed the operation. These bits are invalid for targets that are selected under the single initiator option of the SCSI-1 speciﬁcation.
Page 153 Reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register in case additional interrupts are pending (the LSI53C896 SCSI functions stack interrupts). The DIP bit in the Interrupt Status Zero (ISTAT0) register is also cleared.
Page 154 MDPE Master Data Parity Error This bit is set when the LSI53C896 SCSI function as a master detects a data parity error, or a target device signals a parity error during a data phase. This bit is completely disabled by the Master Parity Error Enable bit...
Page 155 Data (bit 18) and Compare Phase (bit 17) bits are set in the DMA Byte Counter (DBC) register while the LSI53C896 SCSI function is in target mode. • During a Transfer Control instruction, the Carry Test bit (bit 21) is set and either the Compare Data (bit 18) or Compare Phase (bit 17) bit is set.
Page 156 Register: 0x0D SCSI Status Zero (SSTAT0) Read Only SDP0 SIDL Least Signiﬁcant Byte Full This bit is set when the least signiﬁcant byte in the SCSI Input Data Latch (SIDL) contains data. Data is transferred from the SCSI bus to the SCSI Input Data Latch register before being sent to the DMA FIFO and then to the host bus.
Page 157 Arbitration in Progress Arbitration in Progress (AIP = 1) indicates that the LSI53C896 SCSI function has detected a Bus Free condition, asserted SBSY, and asserted its SCSI ID onto the SCSI bus. Lost Arbitration When set, LOA indicates that the LSI53C896 SCSI...
Page 158 Table 4.6 SCSI Synchronous Data FIFO Word Count Bytes or Words in the (SSTAT2 bit 4) SCSI FIFO 4-46 Registers...
Page 159 SDP0L Latched SCSI Parity This bit reﬂects the SCSI parity signal (SDP0/), corresponding to the data latched in the SCSI Input Data Latch (SIDL). It changes when a new byte is latched into the least signiﬁcant byte of the SIDL register. This bit is active HIGH, in other words, it is set when the parity signal is active.
Page 160 DIFF Diffsens Mismatch This bit is set when the DIFFSENS pin detects a SE or LVD SCSI operating voltage level while the LSI53C896 is operating in HVD mode (by setting the DIF bit in the SCSI Test Two (STEST2) register).
Page 161 ABRT Aborted Setting this bit aborts the current operation under execution by the LSI53C896 SCSI function. If this bit is set and an interrupt is received, clear this bit before reading the DMA Status (DSTAT) register to prevent further aborted interrupts from being generated.
Page 162 SRST Software Reset Setting this bit resets the LSI53C896 SCSI function. All operating registers are cleared to their respective default values and all SCSI signals are deasserted. Setting this bit does not assert the SCSI RST/ signal. This reset does not clear the ID Mode bit or any of the PCI conﬁguration...
Page 163 The SCRIPTS processor may set this bit using a SCRIPTS register write instruction. An external processor may also set it while the LSI53C896 SCSI function is executing a SCRIPTS operation. This bit enables the SCSI function to notify an external processor of a predeﬁned condition while SCRIPTS are running.
Page 164 SCSI Interrupt Pending This status bit is set when an interrupt condition is detected in the SCSI portion of the LSI53C896 SCSI function. The following conditions cause a SCSI interrupt to occur: • A phase mismatch (initiator mode) or SATN/ becomes active (target mode) •...
Page 165 Register: 0x15 Interrupt Status One (ISTAT1) Read/Write FLSH SRUN Reserved [7:3] FLSH Flushing Reading this bit monitors if the chip is currently ﬂushing data. If set, the chip is ﬂushing data from the DMA FIFO. If cleared, no ﬂushing is occurring. This bit is read only and writes will have no effect on the value of this bit.
Page 166 Register: 0x16 Mailbox Zero (MBOX0) Read/Write MBOX0 MBOX0 Mailbox Zero [7:0] These are general purpose bits that may be read or written while SCRIPTS are running. They also may be read or written by the SCRIPTS processor. Note: The host and the SCRIPTS processor code could potentially attempt to access the same mailbox byte at the same time.
Page 167 Register: 0x18 Chip Test Zero (CTEST0) Read/Write Byte Empty in DMA FIFO [7:0] These bits identify the bottom bytes in the DMA FIFO that are empty. Each bit corresponds to a byte lane in the DMA FIFO. For example, if byte lane three is empty, then FMT3 will be set.
Page 168 Register: 0x1A Chip Test Two (CTEST2) Read Only (bit 3 write) DDIR SIGP PCICIE TEOP DREQ DACK DDIR Data Transfer Direction This status bit indicates which direction data is being transferred. When this bit is set, the data is transferred from the SCSI bus to the host bus.
Page 169 TEOP SCSI True End of Process This bit indicates the status of the LSI53C896 SCSI function’s internal TEOP signal. The TEOP signal acknowledges the completion of a transfer through the SCSI portion of the LSI53C896 SCSI function. When this bit is set, TEOP is active.
Page 170 Chip Test Five (CTEST5) register, determines the direction of the transfer. This bit is not self-clearing; clear it once the data is successfully transferred by the LSI53C896 SCSI function. Note: Polling of FIFO ﬂags is allowed during ﬂush operations. Clear DMA FIFO When this bit is set, all data pointers for the DMA FIFO are cleared.
Page 171 Pointer (DSP) register when a Return instruction is executed. This address points to the next instruction to execute. Do not write to this register while the LSI53C896 SCSI function is executing SCRIPTS. During any Memory-to-Memory Move operation, the contents of this register are preserved. The power-up value of this register is indeterminate.
Page 172 while data is being transferred between the two cores. Once the chip has stopped transferring data, these bits are stable. DMA FIFO (DFIFO) register counts the number of bytes transferred between the DMA core and the SCSI core. The DMA Byte Counter (DBC) register counts the number of bytes transferred across the host bus.
Page 173 FBL[2:0] BDIS Burst Disable When set, this bit causes the LSI53C896 SCSI function to perform back to back cycles for all transfers. When this bit is cleared, back to back transfers for opcode fetches and burst transfers for data moves are performed.
Page 174 LSI53C896 SCSI function is informed of the error by the PERR/ pin being asserted by the target. When this bit is cleared, the LSI53C896 SCSI function does not interrupt if a master parity error occurs. This bit is cleared at power-up.
Page 175 Register: 0x22 Chip Test Five (CTEST5) Read/Write ADCK BBCK MASR DDIR BO[9:8] ADCK Clock Address Incrementor Setting this bit increments the address pointer contained in the DMA Next Address (DNAD) register. The DNAD register is incremented based on the DNAD contents and the current DMA Byte Counter (DBC) value.
Page 176 Burst Length Bit 2 This bit works with bits 6 and 7 (BL[1:0]) in the Mode (DMODE), 0x38 register to determine the burst length. For complete deﬁnitions of this ﬁeld, refer to the descriptions of DMODE bits 6 and 7. This bit is disabled if an 112-byte FIFO is selected by clearing the DMA FIFO Size bit.
Page 177 DMA FIFO from memory. While receiving data from the SCSI bus, the counter decrements as data is written to memory from the LSI53C896 SCSI function. The DBC counter decrements each time data is transferred on the PCI bus. It is decremented by an amount equal to the number of bytes that are transferred.
Page 178 DCMD DCMD DMA Command [7:0] This 8-bit register determines the instruction for the LSI53C896 SCSI function to execute. This register has a different format for each instruction. For a complete description see Chapter 5, “SCSI SCRIPTS Instruction Set.” Registers: 0x28–0x2B...
Page 179 normal SCRIPTS operation, once the starting address of the SCRIPTS is written to this register, SCRIPTS are automatically fetched and executed until an interrupt condition occurs. In the single step mode, there is a single step interrupt after each instruction is executed. The DMA SCRIPTS Pointer (DSP) register does not need to be written with...
Page 180 This value is also independent of the width (64 or 32 bits) of the data transfer on the PCI bus. The LSI53C896 SCSI function asserts the Bus Request (REQ/) output when the DMA FIFO can accommodate a transfer of at least one burst threshold of data. Bus...
Page 181 Request (REQ/) is also asserted during start-of-transfer and end-of-transfer cleanup and alignment, even if less than a full burst of transfers is performed. The LSI53C896 SCSI function inserts a “fairness delay” of four CLKs between burst transfers (as set in BL[2:0]) during normal operation.
Page 182 Multiple command is used on all read cycles when it is legal. Burst Opcode Fetch Enable Setting this bit causes the LSI53C896 SCSI function to fetch instructions in burst mode. Speciﬁcally, the chip bursts in the ﬁrst two Dwords of all instructions using a single bus ownership.
Page 183 and executing SCSI SCRIPTS when the DMA SCRIPTS Pointer (DSP) register is written. This bit normally is not used for SCSI SCRIPTS operations. Register: 0x39 DMA Interrupt Enable (DIEN) Read/Write MDPE ABRT Reserved MDPE Master Data Parity Error Bus Fault ABRT Aborted Single Step Interrupt...
Page 184 CLSE PFEN IRQM IRQD CLSE Cache Line Size Enable Setting this bit enables the LSI53C896 SCSI function to sense and react to cache line boundaries set up by the DMA Mode (DMODE) or PCI Cache Line Size register, whichever contains the smaller value. Clearing this bit...
Page 185 8 Dwords of instructions and instruction operands in bursts of 4 or 8 Dwords. Prefetching instructions allows the LSI53C896 SCSI function to make more efﬁcient use of the system PCI bus, thus improving overall system performance. The unit will ﬂush whenever the PFF bit is...
Page 186 SCRIPTS Pointer (DSP) register when this bit is set. This bit is required if the LSI53C896 SCSI function is in one of the following modes: • Manual start mode – Bit 0 in the...
Page 187 LSI53C700 family; selection/reselection IDs are stored in both the SCSI Selector ID (SSID) SCSI First Byte Received (SFBR) registers. This bit is not affected by a software reset. If the COM bit is cleared, do not access this register using SCRIPTS operation as nondeterminate operations may occur.
Page 188 Function Complete Indicates full arbitration and selection sequence is completed. Selected Indicates the LSI53C896 SCSI function is selected by a SCSI initiator device. Set the Enable Response to Selection bit in the SCSI Chip ID (SCID) register for this to occur.
Page 189 SCSI synchronous receive FIFO. Unexpected Disconnect This condition only occurs in the initiator mode. It happens when the target to which the LSI53C896 SCSI function is connected disconnects from the SCSI bus unexpectedly. See the SCSI Disconnect Unexpected bit in the...
Page 190 [7:5] SBMC SCSI Bus Mode Change Setting this bit allows the LSI53C896 to generate an interrupt when the DIFFSENS pin detects a change in voltage level that indicates the SCSI bus has changed between SE, LVD, or HVD modes. For example, when...
Page 191 Reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register because additional interrupts may be pending (the LSI53C896 SCSI functions stack interrupts). SCSI interrupt conditions are individually masked through the SCSI Interrupt Enable Zero (SIEN0) register.
Page 192 This bit is set when an arbitration only or full arbitration sequence is completed. Selected This bit is set when the LSI53C896 SCSI function is selected by another SCSI device. The Enable Response to Selection bit must be set in the...
Page 193 FIFO. Unexpected Disconnect This bit is set when the LSI53C896 SCSI function is operating in the initiator mode and the target device unexpectedly disconnects from the SCSI bus. This bit is only valid when the LSI53C896 SCSI function operates in the initiator mode.
Page 194 SE, LVD or HVD modes. Reserved Selection or Reselection Time-Out The SCSI device which the LSI53C896 SCSI function is attempting to select or reselect does not respond within the programmed time-out period. See the description of SCSI Timer Zero (STIME0) register, bits [3:0], for more information on the time-out timer.
Page 195 Register: 0x44 SCSI Longitudinal Parity (SLPAR) Read/Write SLPAR SLPAR SCSI Longitudinal Parity [7:0] This register performs a bytewise longitudinal parity check on all SCSI data received or sent through the SCSI core. If one of the bytes received or sent (usually the last) is the set of correct even parity bits, SLPAR should go to zero (assuming it started at zero).
Page 196 The longitudinal parity checks are meant to provide an added measure of SCSI data integrity and are entirely optional. This register does not latch SCSI selection/reselection IDs under any circumstances. The default value of this register is zero. The longitudinal parity function normally operates as a byte function.
Page 197 Register: 0x46 Chip Type (CTYPE) Read Only Chip Type [7:4] These bits identify the chip type for software purposes. Note: These bits no longer identify an 8XX device. These bits have been set to 0xF to indicate that the device should be uniquely identiﬁed by setting the PCI Conﬁguration Enable bit in the Chip Test Two (CTEST2)
Page 198 6 of GPCNTL is cleared and the chip is not in progress of performing an EEPROM autodownload regardless of the state of bit 0 (GPIO0). This provides a hardware solution to driving a SCSI activity LED in many implementations of LSI Logic SCSI chips. GPIO GPIO Enable [4:2]...
Page 199 HTH[7:4], SEL[3:0], GEN[3:0] Minimum Time-Out (40 or 160 MHz) 0000 Disabled 125 µs 0001 250 µs 0010 500 µs 0011 0100 1 ms 0101 2 ms 0110 4 ms 0111 8 ms 1000 16 ms 1001 32 ms 1010 64 ms 1011 128 ms 1100...
Page 200 Register: 0x49 SCSI Timer One (STIME1) Read/Write HTHBA GENSF HTHSF GEN[3:0] Reserved HTHBA Handshake-to-Handshake Timer Bus Activity Enable Setting this bit causes this timer to begin testing for SCSI REQ/ and ACK/ activity as soon as SBSY/ is asserted, regardless of the agents participating in the transfer. GENSF General Purpose Timer Scale Factor Setting this bit causes this timer to shift by a factor of 16.
Page 201 Minimum Time-out HTH[7:4], SEL[3:0], (50 MHz Clock) GEN[3:0] HTHSF = 0, HTHSF = 1, GENSF = 0 GENSF = 1 0000 Disabled Disabled 100 µs 0001 1.6 ms 200 µs 0010 3.2 ms 400 µs 0011 6.4 ms 800 µs 0100 12.8 ms 0101...
Page 202 Minimum Time-out (40 or 160 MHz Clock) HTH[7:4], SEL[3:0], HTHSF = 0, HTHSF = 1, GEN[3:0] GENSF = 0 GENSF = 1 0000 Disabled Disabled 125 µs 0001 2 ms 250 µs 0010 4 ms 500 µs 0011 8 ms 1 µs 0100 16 ms...
Page 203 Register: 0x4A Response ID Zero (RESPID0) Read/Write RESPID0 Response ID Zero [7:0] RESPID0 and Response ID One (RESPID1) contain the selection or reselection IDs. In other words, these two 8-bit registers contain the ID that the chip responds to on the SCSI bus.
Page 204 SCSI selection or reselection phase. These bits are read only and contain the encoded value of 0–15 possible IDs that could be used to select the LSI53C896 SCSI function. During a SCSI selection or reselection phase when a valid ID is put on the bus, and the LSI53C896 SCSI function responds to that ID, the “selected as”...
Page 205 It is used in low level synchronous SCSI operations. When this bit is set, the LSI53C896 SCSI is functioning as a target, and is waiting for the initiator to acknowledge the data transfers. If the LSI53C896 SCSI is functioning as an initiator, then the target has sent the offset number of requests.
Page 206 SCSI clock. IRM[1:0] Interrupt Routing Mode [1:0] The LSI53C896 supports four different interrupt routing modes. These modes are described in the following table. Each SCSI core within the chip can be conﬁgured independently. Mode 0 is the default mode and is compatible with AMI RAID upgrade products.
Page 207 SCSI Output Control Latch (SOCL) SCSI Output Data Latch (SODL) registers regardless of whether the LSI53C896 SCSI function is conﬁgured as a target or initiator. Note: Do not set this bit during normal operation, since it could cause contention on the SCSI bus.
Page 208 SCSI Low level Mode Setting this bit places the LSI53C896 SCSI function in low level mode. In this mode, no DMA operations occur, and no SCRIPTS execute. Arbitration and selection may...
Page 209 LSI53C896 SCSI function is driving these signals. Active deassertion of these signals occurs only when the LSI53C896 SCSI function is in an information transfer phase. When operating in a differential environment or at fast SCSI timings, TolerANT Active negation should be enabled to improve setup and deassertion times.
Page 210 Disable Single Initiator Response If this bit is set, the LSI53C896 SCSI function ignores all bus-initiated selection attempts that employ the single initiator option from SCSI-1. In order to select the LSI53C896 SCSI function while this bit is set, the LSI53C896 SCSI function’s SCSI ID and the initiator’s...
Page 211 SCSI Output Data Latch (SODL) register and then read back into the LSI53C896 by reading this register to allow loopback testing. When receiving SCSI data, the data ﬂows into this register and out to the host FIFO. This register differs...
Page 212 Frequency Lock This bit is used when enabling the SCSI clock quadrupler, which allows the LSI53C896 to transfer data at Ultra2 SCSI rates. Poll this bit for a 1 to determine that the clock quadrupler has locked to 160 MHz. For more information...
Page 213 Registers: 0x54–0x55 SCSI Output Data Latch (SODL) Read/Write SODL SODL SCSI Output Data Latch [15:0] This register is used primarily for diagnostic testing or programmed I/O operation. Data written to this register is asserted onto the SCSI data bus by setting the Assert Data Bus bit in the SCSI Control One (SCNTL1) register.
Page 214 (PMJAD2) when the WSR bit is set. When this bit is set the LSI53C896 will use jump address one (PMJAD1) on data out (data out, command, message out) transfers and jump address two (PMJAD2) on data in (data in, status, message in) transfers.
Page 215 MOE/_TESTOUT, into a high impedance state. When this bit is set, the MOE/_TESTOUT pin becomes the output pin for the connectivity test of the LSI53C896 signals in the “AND-tree” test mode. In order to read data out of the LSI53C896 SCSI function, this bit must be cleared. This bit is intended for board-level testing only.
Page 216 When this bit is set, all 64-bit addressing as a master will be disabled. No DACs will be generated by the LSI53C896. When this bit is cleared, the LSI53C896 will generate DACs based on the master operation being performed and the value of its associated selector register.
Page 217 Registers: 0x58–0x59 SCSI Bus Data Lines (SBDL) Read Only SBDL SBDL SCSI Bus Data Lines [15:0] This register contains the SCSI data bus status. Even though the SCSI data bus is active LOW, these bits are active HIGH. The signal status is not latched and is a true representation of exactly what is on the data bus at the time the register is read.
Page 218 enabled by setting the PCI Conﬁguration Info Enable bit in the Chip Test Two (CTEST2) register. If this bit is set, Scratch Register B (SCRATCHB) returns bits [31:13] of the SCRIPTS RAM PCI Base Address Register Two (SCRIPTS RAM) in bits [31:13] of the SCRATCH B register when read.
Page 219: 64-Bit Scripts Selectors
4.3 64-Bit SCRIPTS Selectors The following registers are used to hold the upper 32-bit addresses for various SCRIPTS operations. When a particular type of SCRIPTS operation is performed, one of the 6 selector registers below will be used to generate a 64-bit address. If the selector for a particular device operation is zero, then a standard 32-bit address cycle will be generated.
Page 220 Writes to the MMRS register are unaffected. Clearing the PCI Conﬁguration Info Enable bit causes the MMRS register to return to normal operation. Registers: 0xA4–0xA7 Memory Move Write Selector (MMWS) Read/Write MMWS MMWS Memory Move Write Selector [31:0] Supplies AD[63:32] during data write operations during Memory-to-Memory Moves and absolute address STORE operations.
Page 221 SCRIPTS Fetch Selector (SFS) register return the PCI Revision ID (Rev ID) register value and bits [0:15] return the PCI Device ID register value when read. Writes to the SCRIPTS Fetch Selector (SFS) register are unaffected. Clearing the PCI Conﬁguration Information Enable bit causes the SFS register to return to normal operation.
Page 222 Registers: 0xB4–0xB7 Dynamic Block Move Selector (DBMS) Read/Write DBMS DBMS Dynamic Block Move Selector [31:0] Supplies AD[63:32] during block move operations, reads or writes. This register is used only during 64-bit direct BMOV instructions and will be reloaded with the upper 32-bit data address upon execution of 64-bit direct BMOVs.
Page 223: Phase Mismatch Jump Registers
4.4 Phase Mismatch Jump Registers Eight 32-bit registers contain the byte count and addressing information required to update the direct, indirect, or table indirect BMOV instructions with new byte counts and addresses. The eight register descriptions follow. All registers can be read/written using the Load/Store SCRIPTS instructions, Memory-to-Memory Moves, read/write SCRIPTS instructions, or the CPU with SCRIPTS not running.
Page 224 state of the PMJCTL bit this address will either be used during an inbound (data in, status, message in) phase mismatch (PMJCTL = 0) or when the WSR bit is set (PMJCTL = 1). It should be loaded with an address of a SCRIPTS routine that will handle the updating of memory data structures of the BMOV that was executing when the phase mismatch occurred.
Page 225 Registers: 0xCC–0xCF Updated Address (UA) Read/Write Updated Address [31:0] This register will contain the updated data address for the BMOV that was executing when the phase mismatch occurred. In the case of a SCSI data receive, if there is a byte in SCSI Wide Residue (SWIDE) register then this address will point to the location where that byte must be...
Page 226 Registers: 0xD0–0xD3 Entry Storage Address (ESA) Read/Write Entry Storage Address [31:0] This register's value depends on the type of BMOV being executed. The three types of BMOVs are. Direct BMOV: In the case of a direct BMOV, this register will contain the address the BMOV was fetched from when the phase mismatch occurred.
Page 227 Registers: 0xD8–0xDA SCSI Byte Count (SBC) Read Only SCSI Byte Count [23:0] This register contains the count of the number of bytes transferred to or from the SCSI bus during any given BMOV. This value is used in calculating the information placed into the Remaining Byte Count (RBC) Updated Address (UA)
Page 228 the SCSI bus during data phases, i.e. it will not count bytes sent in command, status, message in or message out phases. It will count bytes as long as the phase mismatch enable (ENPMJ) in the Chip Control 0 (CCNTL0) register is set.
Page 229: Scsi Scripts Instruction Set
Section 5.7, “Load/Store Instructions” 5.1 SCSI SCRIPTS To operate in the SCSI SCRIPTS mode, the LSI53C896 requires only a SCRIPTS start address. The start address must be at a Dword (four byte) boundary. This aligns all the following SCRIPTS at a Dword boundary since all SCRIPTS are 8 or 12 bytes long.
Page 230 In the SCSI SCRIPTS mode the LSI53C896 is allowed to make decisions based on the status of the SCSI bus, which frees the microprocessor from servicing the numerous interrupts inherent in I/O operations.
Page 231: Sample Operation
LSI53C896 requests use of the PCI bus again to transfer the data. • When the LSI53C896 is granted the PCI bus, it executes (as a bus master) a burst transfer (programmable size) of data, decrements the internally stored remaining byte count, increments the address pointer, and then releases the PCI bus.
Page 232: Block Move Instructions
In this manner, the LSI53C896 performs scatter/gather operations on data without requiring help from the host program, generating a host interrupt, or programming of an external DMA controller. An overview of this process...
Page 233: First Dword
5.2.1 First Dword Figure 5.2 Block Move Instruction - First Dword DCMD Register DBC Register IT[1:0] TIA OPC SCSIP[2:0] TC[23:0] IT[1:0] Instruction Type-Block Move [31:30] Indirect Addressing Direct When this bit is cleared, user data is moved to or from the 32-bit data start address for the Block Move instruction.
Page 234 Use the fetched byte count, but fetch the data address from the address in the instruction. If 64-bit addressing is desired, the upper Dword of the address is stored in the Static Block Move Selector (SBMS) register. When the value in SBMS is 0x0, 32-bit addressing is assumed.
Page 235 For a MOVE instruction, the 24-bit byte count is fetched from system memory. Then the 32-bit physical address is brought into the LSI53C896. Execution of the move begins at this point. SCRIPTS can directly execute operating system I/O data structures, saving time at the beginning of an I/O operation.
Page 236 If the enable 64-bit Table Indirect Block Move (EN64TIBMV) bit is set and the 64-bit Table Indirect Index Mode (64TIMOD) bit is cleared, then bits [28:24] of the ﬁrst Dword of the table entry (where the byte count is located) will select one of the 16 scratch registers or any of the six 64-bit selector registers (for a total of 22 selector choices) as a selector for the upper 32-bit address.
Page 237 Upper 32-Bit Data EN64TIBMV 64TIMOD Address Comes From SBMS SBMS ScratchC–J, MMWS, MMRS, SFS, DRS, SBMS, DBMS 1st Table Entry Dword bits 24–31 (40-bit addressing only) Table Indirect Index mode mapping: Index Value Selector Used 0x00 Scratch C 0x01 Scratch D 0x02 Scratch E 0x03...
Page 238 Instruction Deﬁned MOVE/MOVE64 CHMOV/CHMOV64 The LSI53C896 veriﬁes that it is connected to the SCSI bus as a target before executing this instruction. The LSI53C896 asserts the SCSI phase signals (SMSG/, SC_D/, and SI_O/) as deﬁned by the Phase Field bits in the instruction.
Page 239 DMA Next Address (DNAD) register. If the Opcode bit is set and a data transfer ends on an odd byte boundary, the LSI53C896 stores the last byte in the SCSI Wide Residue (SWIDE) register during a receive operation.
Page 240 DMA Next Address (DNAD) register. If the opcode bit is cleared and a data transfer ends on an odd byte boundary, the LSI53C896 stores the last byte in the SCSI Wide Residue (SWIDE) register during a receive...
Page 241 TC[23:0] Transfer Counter [23:0] This 24-bit ﬁeld speciﬁes the number of data bytes to be moved between the LSI53C896 and system memory. The ﬁeld is stored in the DMA Byte Counter (DBC) register. When the LSI53C896 transfers data to/from memory, the DBC register is decremented by the number of bytes transferred.
Page 242: Second Dword
This 32-bit ﬁeld speciﬁes the starting address of the data to move to/from memory. This ﬁeld is copied to the Next Address (DNAD) register. When the LSI53C896 transfers data to or from memory, the DNAD register is incremented by the number of bytes transferred.
Page 243: I/O Instructions
[31:30] OPC[2:0] Opcode [29:27] The following Opcode bits have different meanings, depending on whether the LSI53C896 is operating in the initiator or target mode. Opcode selections 0b101–0b111 are considered Read/Write instructions, and are described Section 5.4, “Read/Write Instructions.” Target Mode OPC2 OPC1 OPC0 Instruction Deﬁned...
Page 244 32-bit jump address ﬁeld stored in the DMA Next Address (DNAD) register. Manually set the LSI53C896 to the initiator mode if it is reselected, or to the target mode if it is selected. Disconnect Instruction The LSI53C896 disconnects from the SCSI bus by deasserting all SCSI signal outputs.
Page 245 If it loses arbitration, it tries again during the next available arbitration cycle without reporting any lost arbitration status. If the LSI53C896 wins arbitration, it attempts to select the SCSI device whose ID is deﬁned in the destination ID ﬁeld of the instruction. Once the LSI53C896 wins...
Page 246 DMA Next Address (DNAD) register. Manually set the LSI53C896 to the initiator mode if it is reselected, or to the target mode if it is selected. If the Select with SATN/ ﬁeld is set, the SATN/ signal is asserted during the selection phase.
Page 247 cleared, the corresponding bit in the SCSI Control Zero (SCNTL0) register is cleared. When the carry bit is cleared, the corresponding bit in the ALU is cleared. Relative Addressing Mode When this bit is set, the 24-bit signed value in the Next Address (DNAD) register is used as a relative displacement from the current...
Page 248 Conﬁg Offset/period Use this bit only in conjunction with the Select, Reselect, Wait Select, and Wait Reselect instructions. It is allowable to set bits 25 and 26 individually or in combination: Bit 25 Bit 26 Direct Table Indirect Relative Table Relative Direct Uses the device ID and physical address in the instruction.
Page 249 This bit is used in conjunction with a Set or Clear instruction to set or clear the target mode. Setting this bit with a Set instruction conﬁgures the LSI53C896 as a target device (this sets bit 0 of the SCSI Control Zero (SCNTL0) register).
Page 250: Second Dword
Since SACK/ and SATN/ are initiator signals, they are not asserted on the SCSI bus unless the LSI53C896 is operating as an initiator or the SCSI Loopback Enable bit is set in the SCSI Test Two (STEST2) register.
Page 251: Read/Write Instructions
A[6:0] Register Address - A[6:0] [22:16] It is possible to change register values from SCRIPTS in read-modify-write cycles or move to/from SCSI First Byte Received (SFBR) cycles. A[6:0] selects an 8-bit source/destination register within the LSI53C896. Read/Write Instructions 5-23...
Page 252: Second Dword
ImmD Immediate Data [15:8] This 8-bit value is used as a second operand in logical and arithmetic functions. Upper Register Address Line [A7] This bit is used to access registers 0x80–0xFF. Reserved [6:0] 5.4.2 Second Dword Figure 5.8 Read/Write Instruction - Second Dword DSPS Register Destination Address [31:0]...
Page 253 • Write one byte (value contained within the SCRIPTS instruction) into any chip register. • Move to/from the SCSI First Byte Received (SFBR) from/to any other register. • Alter the value of a register with AND, OR, ADD, XOR, SHIFT LEFT, or SHIFT RIGHT operators.
Page 254: Transfer Control Instructions
Table 5.1 Read/Write Instructions (Cont.) Opcode 111 Opcode 110 Opcode 101 Operator Read-Modify-Write Move to SFBR Move from SFBR Shift register one bit to the Shift register one bit to the Shift the SFBR register one right and place the result in right and place the result in bit to the right and place the the same register.
Page 255: First Dword
Interrupt Reserved Jump Instruction The LSI53C896 can do a true/false comparison of the ALU carry bit, or compare the phase and/or data as deﬁned by the Phase Compare, Data Compare and True/False bit ﬁelds. If the comparisons are true, then it...
Page 256 32-bit address (0) or a 64-bit address (1). All combinations of jumps are still valid for JUMP64. Call Instruction The LSI53C896 can do a true/false comparison of the ALU carry bit, or compare the phase and/or data as deﬁned by the Phase Compare, Data Compare, and True/False bit ﬁelds.
Page 257 If the comparisons are false, the LSI53C896 fetches the next instruction from the address pointed to by the SCRIPTS Pointer (DSP) register and the instruction pointer is not modiﬁed. Interrupt Instruction The LSI53C896 can do a true/false comparison of the ALU carry bit, or compare the phase and/or data as deﬁned by the Phase Compare, Data Compare, and...
Page 258 The SCRIPTS program counter is a 32-bit value pointing to the SCRIPTS currently under execution by the LSI53C896. The next address is formed by adding the 32-bit program counter to the 24-bit signed value of the last 24 bits of the Jump or Call instruction. Because it is signed (2’s complement), the jump can be forward or...
Page 259 (Interrupt Status Zero (ISTAT0), bit 2) is asserted. Jump If True/False This bit determines whether the LSI53C896 branches when a comparison is true or when a comparison is false. This bit applies to phase compares, data compares, and carry tests. If both the Phase Compare and Data Compare bits are set, then both compares must be true to branch on a true condition.
Page 260 SCSI SATN/ signal. Wait For Valid Phase If the Wait for Valid Phase bit is set, the LSI53C896 waits for a previously unserviced phase before comparing the SCSI phase and data.
Page 261: Second Dword
This 32-bit ﬁeld contains the address of the next instruction to fetch when a jump is taken. Once the LSI53C896 fetches the instruction from the address pointed to by these 32 bits, this address is incremented by 4, loaded into the DMA SCRIPTS Pointer (DSP) register and becomes the current instruction pointer.
Page 262: Memory Move Instructions
Memory Move Write Selector (MMWS) register. Allowing the LSI53C896 to perform memory moves frees the system processor for other tasks and moves data at higher speeds than available from current DMA controllers. Up to 16 Mbytes may be transferred with one instruction.
Page 263: First Dword
These bits are reserved and must be zero. If any of these bits are set, an illegal instruction interrupt occurs. No Flush When this bit is set, the LSI53C896 performs a Memory Move without ﬂushing the prefetch unit. When this bit is cleared, the Memory Move instruction automatically ﬂushes the prefetch unit.
Page 264: Second Dword
Memory Move. However, it can be loaded using SCRIPTS Read/Write operations. To load the SFBR with a byte stored in system memory, ﬁrst move the byte to an intermediate LSI53C896 register (for example, a SCRATCH register), and then to the...
Page 265: Third Dword
5.6.4 Third Dword Figure 5.14 Memory Move Instructions - Third Dword TEMP Register TEMP Register [31:0] These bits contain the destination address for the Memory Move. If the destination address is in the 64-bit address space, the bits will be contained in the Memory Move Write Selector (MMWS) register.
Page 266: First Dword
A maximum of 4 bytes may be moved with these instructions. The register address and memory address must have the same byte alignment, and the count set such that it does not cross Dword boundaries. The memory address may not map back to the chip, excluding RAM and ROM.
Page 267 Reserved [27:26] No Flush (Store instruction only) When this bit is set, the LSI53C896 performs a Store without ﬂushing the prefetch unit. When this bit is cleared, the Store instruction automatically ﬂushes the prefetch unit. Use No Flush if the source and destination are not within four instructions of the current Store instruction.
Page 268: Second Dword
5.7.2 Second Dword Figure 5.16 Load/Store Instructions - Second Dword 24 23 DSPS Register - Memory I/O Address/DSA Offset 24 23 MMRS/MMWS Register Memory I/O Address / DSA Offset [31:0] This is the actual memory location of where to load/store, or the offset from the Data Structure Address (DSA) register value.
Page 269: Dc Characteristics
• Section 6.4, “PCI and External Memory Interface Timing Diagrams” • Section 6.5, “SCSI Timing Diagrams” 6.1 DC Characteristics This section of the manual describes the LSI53C896 DC characteristics. Table 6.1 through Table 6.12 give current and voltage speciﬁcations. Figure 6.1 Figure 6.2...
Page 270 Table 6.1 Absolute Maximum Stress Ratings Symbol Parameter Unit Test Conditions −55 °C Storage temperature – −0.5 Supply voltage – −0.3 Input voltage +0.3 – −0.3 Input voltage (5 V tolerant pins) V 5.25 – IN5V ±150 Latch-up current – –...
Page 271 Table 6.3 LVD Driver SCSI Signals—SD[15:0], SDP[1:0], SREQ/, SREQ2/, SACK/, SACK2/, SMSG/, SIO/, SCD/, SATN/, SBSY/, SSEL/, SRST/ Symbol Parameter Units Test Conditions −7 −13 Source (+) current Asserted state − Sink (−) current Asserted state Source (+) current Negated state −...
Page 272 Figure 6.2 LVD Receiver − − − − Table 6.5 A and B DIFFSENS SCSI Signals Symbol Parameter Unit Test Conditions HVD sense voltage Note 1 LVD sense voltage Note 1 −0.3 SE sense voltage Note 1 −10 µA Input leakage = 0 V, 5.25 V 1.
Page 273 Table 6.7 Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/, GPIO2, GPIO3, GPIO4, MAD[7:0] Symbol Parameter Unit Test Conditions Input high voltage – −0.3 Input low voltage – −8 mA dynamic Output high voltage Output low voltage 8 mA dynamic −10 µA 3-state leakage = 0 V, 5.25 V µA Pull down current –...
Page 274 Table 6.9 Bidirectional Signals—AD[63:0], C_BE[7:0]/, FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR, PAR64, REQ64/, ACK64/ Symbol Parameters Unit Test Conditions Input high voltage 0.5 V – Input low voltage -0.3 0.3 V – −500 µA Output high voltage 0.9 V –...
Page 275 Table 6.11 Output Signals—INTA, INTB, ALT_INTA, ALT_INTB, REQ/ Symbol Parameters Unit Test Conditions −500 µA Output high voltage 0.9 V – 1500 µA Output low voltage – 0.1 V −16 mA 5 V Tolerant output high voltage – 5 V Tolerant output low voltage –...
Page 276: Tolerant Technology Electrical Characteristics
6.2 TolerANT Technology Electrical Characteristics The LSI53C896 features TolerANT technology, which includes active negation on the SCSI drivers and input signal ﬁltering on the SCSI receivers. Active negation actively drives the SCSI Request, Acknowledge, Data, and Parity signals HIGH rather than allowing them to be passively pulled up by terminators.
Page 277 Table 6.13 TolerANT Technology Electrical Characteristics for SE SCSI Signals Symbol Parameter Units Test Conditions Rise time, 10% to 90% 18.5 Figure 6.3 Fall time, 90% to 10% 18.5 Figure 6.3 Slew rate LOW to HIGH 0.15 0.50 V/ns Figure 6.3 Slew rate HIGH to LOW 0.15 0.50...
Page 278 Figure 6.5 Hysteresis of SCSI Receivers Input Voltage (Volts) Figure 6.6 Input Current as a Function of Input Voltage 14.4 V 8.2 V −0.7 V HIGH-Z OUTPUT −20 ACTIVE −40 −4 Input Voltage (Volts) 6-10 Speciﬁcations...
Page 279: Ac Characteristics
Figure 6.7 Output Current as a Function of Output Voltage −200 −400 −600 −800 Output Voltage (Volts) Output Voltage (Volts) 6.3 AC Characteristics The AC characteristics described in this section apply over the entire range of operating conditions (refer to Section 6.1, “DC Characteristics”).
Page 280 Table 6.14 External Clock Symbol Parameter Units Bus clock cycle time SCSI clock cycle time (SCLK) CLK LOW time – SCLK LOW time CLK HIGH time – SCLK HIGH time CLK slew rate – V/ns SCLK slew rate – V/ns 1.
Page 281 Table 6.15 Figure 6.9 provide Reset Input timing data. Table 6.15 Reset Input Symbol Parameter Units Reset pulse width – Reset deasserted setup to CLK HIGH – MAD setup time to CLK HIGH (for conﬁguring – the MAD bus only) MAD hold time from CLK HIGH (for conﬁguring –...
Page 282: Pci And External Memory Interface Timing Diagrams
Figures 6.11 through 6.34 represent signal activity when the LSI53C896 accesses the PCI bus. This section includes timing diagrams for access to three groups of memory conﬁgurations. The ﬁrst group applies to Target Timing. The second group applies to Initiator Timing.
Page 283: Target Timing
– Operating Register/SCRIPTS RAM Write, 32-Bit – Operating Register/SCRIPTS RAM Write, 64-Bit • Initiator Timing – Nonburst Opcode Fetch, 32-Bit Address and Data – Burst Opcode Fetch, 32-Bit Address and Data – Back to Back Read, 32-Bit Address and Data –...
Page 284 Addr In AD[31:0] Data Out (Driven by Master-Addr; LSI53C896-Data) C_BE[3:0]/ Byte Enable (Driven by Master) (Driven by Master-Addr; LSI53C896-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C896) STOP/ (Driven by LSI53C896) DEVSEL/ (Driven by LSI53C896) IDSEL (Driven by Master) 6-16 Speciﬁcations...
Page 285 (Driven by Master) C_BE[3:0]/ Byte Enable (Driven by Master) (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C896) STOP/ (Driven by LSI53C896) DEVSEL/ (Driven by LSI53C896) IDSEL (Driven by Master) PCI and External Memory Interface Timing Diagrams 6-17...
Page 286 FRAME/ (Driven by Master) Addr In AD[31:0] Data (Driven by Master-Addr; LSI53C896-Data) C_BE[3:0]/ Byte Enable (Driven by Master) (Driven by Master-Addr; LSI53C896-Data IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C896) STOP/ (Driven by LSI53C896) DEVSEL/ (Driven by LSI53C896) 6-18 Speciﬁcations...
Page 287 Shared signal input hold time – CLK to shared signal output valid – Figure 6.14 Operating Register/SCRIPTS RAM Read, 64-Bit (Driven by System) REQ64/ (Driven by Master) ACK64/ (Driven by LSI53C896) FRAME/ (Driven by Master) AD[31:0] Addr Addr Data (Driven by Master-Addr; LSI53C896-Data)
Page 288 (Driven by System) FRAME/ (Driven by Master) Addr In AD[31:0] Data In (Driven by Master) C_BE[3:0]/ Byte Enable (Driven by Master) (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C896) STOP/ (Driven by LSI53C896) DEVSEL/ (Driven by LSI53C896) 6-20 Speciﬁcations...
Page 289 Shared signal input hold time – CLK to shared signal output valid – Figure 6.16 Operating Register/SCRIPTS RAM Write, 64-Bit (Driven by System) REQ64/ (Driven by Master) ACK64/ (Driven by LSI53C896) FRAME/ (Driven by Master) AD[31:0] Addr Addr Data In (Driven by Master) C_BE[3:0]/...
Page 290: Initiator Timing
6.4.2 Initiator Timing Tables 6.23 through 6.30 and Figures 6.17 6.24 describe Initiator timing. Table 6.23 Nonburst Opcode Fetch, 32-Bit Address and Data Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid Side signal input setup time –...
Page 291 Figure 6.17 Nonburst Opcode Fetch, 32-Bit Address and Data (Driven by System) REQ64/ (Driven by LSI53C896) ACK64/ (Driven by LSI53C896) GPIO0_FETCH/ (Driven by LSI53C896) GPIO1_MASTER/ (Driven by LSI53C896) REQ/ (Driven by LSI53C896) GNT/ (Driven by Arbiter) FRAME/ Data Data (Driven by LSI53C896)
Page 292 Table 6.24 Burst Opcode Fetch, 32-Bit Address and Data Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid Side signal input setup time – Side signal input hold time –...
Page 293 Figure 6.18 Burst Opcode Fetch, 32-Bit Address and Data (Driven by System) REQ64/ (Driven by LSI53C896) ACK64/ (Driven by LSI53C896) GPIO0_FETCH/ (Driven by LSI53C896) GPIO1_MASTER/ (Driven by LSI53C896) REQ/ (Driven by LSI53C896) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C896)
Page 294 Table 6.25 Back to Back Read, 32-Bit Address and Data Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid Side signal input setup time – Side signal input hold time –...
Page 295 Figure 6.19 Back to Back Read, 32-Bit Address and Data (Driven by System) REQ64/ (Driven by LSI53C896) ACK64/ (Driven by LSI53C896) GPIO0_FETCH/ (Driven by LSI53C896) GPIO1_MASTER/ (Driven by LSI53C896) REQ/ (Driven by LSI53C896) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C896)
Page 296 Table 6.26 Back to Back Write, 32-Bit Address and Data Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid Side signal input setup time – Side signal input hold time –...
Page 297 Figure 6.20 Back to Back Write, 32-Bit Address and Data (Driven by System) REQ64/ (Driven by LSI53C896) ACK64/ (Driven by LSI53C896) GPIO0_FETCH/ (Driven by LSI53C896) GPIO1_MASTER/ (Driven by LSI53C896) REQ/ (Driven by LSI53C896) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C896)
Page 298 Table 6.27 Burst Read, 32-Bit Address and Data Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid 6-30 Speciﬁcations...
Page 299 Figure 6.21 Burst Read, 32-Bit Address and Data (Driven by System) GPIO0_FETCH/ (Driven by LSI53C896) GPIO1_MASTER/ (Driven by LSI53C896) REQ/ (Driven by LSI53C896) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C896) Data In AD[31:0] Addr (Driven by LSI53C896- Addr; Target-Data)
Page 300 Table 6.28 Burst Read, 64-Bit Address and Data Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid CLK HIGH to GPIO1_MASTER/ HIGH – 6-32 Speciﬁcations...
Page 301 Data In AD[63:32] (Driven by LSI53C896- Hi Address Addr; Target-Data) C_BE[7:4]/ Bus CMD (Driven by LSI53C896) PAR; PAR64 (Addr drvn by LSI53C896;- Data drvn by Target) IRDY/ (Driven by LSI53C896) TRDY/ (Driven by Target) STOP/ (Driven by Target) DEVSEL/ (Driven by Target)
Page 302 Table 6.29 Burst Write, 32-Bit Address and Data Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid CLK HIGH to GPIO1_MASTER/ HIGH – 6-34 Speciﬁcations...
Page 303 Figure 6.23 Burst Write, 32-Bit Address and Data (Driven by System) GPIO0_FETCH/ (Driven by LSI53C896) GPIO1_MASTER/ (Driven by LSI53C896) REQ/ (Driven by LSI53C896) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C896) AD[31:0] Addr Data Data (Driven by LSI53C896) C_BE[3:0]/ (Driven by LSI53C896)
Page 304 Table 6.30 Burst Write, 64-Bit Address and Data Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid CLK HIGH to GPIO1_MASTER/ HIGH – 6-36 Speciﬁcations...
Page 305 Figure 6.24 Burst Write, 64-Bit Address and Data (Driven by System) GPIO0_FETCH/ (Driven by LSI53C896) GPIO1_MASTER/ (Driven by LSI53C896) REQ/ (Driven by LSI53C896) GNT/ (Driven by Arbiter) REQ64/ (Driven by LSI53C896) ACK64/ (Driven by Target) FRAME/ (Driven by LSI53C896) AD[31:0]...
Page 306 This page intentionally left blank. 6-38 Speciﬁcations...
Page 307: External Memory Timing
6.4.3 External Memory Timing Tables 6.31 through 6.38 and Figures 6.25 through 6.34 describe External Memory timing. Table 6.31 External Memory Read Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid –...
Page 308 (Driven by Master) TRDY/ (Driven by LSI53C896) STOP/ (Driven by LSI53C896) DEVSEL/ (Driven by LSI53C896) High Order Middle Order Low Order (Addr drvn by LSI53C896 Address Address Address Data Driven by Memory) MAS1/ (Driven by LSI53C896) MAS0/ (Driven by LSI53C896) MCE/...
Page 309 IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C896) STOP/ (Driven by LSI53C896) DEVSEL/ (Driven by LSI53C896) Data (Addr drvn by LSI53C896; Data Driven by Memory) MAS1/ (Driven by LSI53C896) MAS0/ (Driven by LSI53C896) MCE/ (Driven by LSI53C896) MOE/ (Driven by LSI53C896)
Page 310 This page intentionally left blank. 6-42 Speciﬁcations...
Page 311: External Memory Write
Table 6.32 External Memory Write Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid – Address setup to MAS/ HIGH – Address hold from MAS/ HIGH – MAS/ pulse width –...
Page 312 Addr Data In (Driven by Master) C_BE[3:0]/ Byte Enable (Driven by Master) (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C896) STOP/ (Driven by LSI53C896) DEVSEL/ (Driven by LSI53C896) High Order Middle Order Low Order Address Address (Driven by LSI53C896)
Page 313 (Driven by Master) AD[31:0] (Driven by Master) C_BE[3:0]/ Byte Enable (Driven by Master) (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C896) STOP/ (Driven by LSI53C896) DEVSEL/ (Driven by LSI53C896) Data Out (Driven by LSI53C896) MAS1/ (Driven by LSI53C896) MAS0/...
Page 314: Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access Read Cycle
Data setup to CLK HIGH – Figure 6.27 Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access Read Cycle (Driven by System) High Order Middle Order Low Order (Addr driven by LSI53C896; Address Address Address Data Driven by Memory) MAS1/ (Driven by LSI53C896)
Page 315 Figure 6.27 Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access Read Cycle (Cont.) (Driven by System) Valid Read (Addr driven by LSI53C896; Data Data Driven by Memory) MAS1/ (Driven by LSI53C896) MAS0/ (Driven by LSI53C896) MCE/ (Driven by LSI53C896) MOE/...
Page 316 MWE/ HIGH to MCE/ HIGH – Figure 6.28 Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access Write Cycle (Driven by System) Valid Middle Order High Order Low Order Write (Driven by LSI53C896) Address Address Address Data MAS1/ (Driven by LSI53C896) MAS0/ (Driven by LSI53C896)
Page 317 Figure 6.28 Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access Write Cycle (Cont.) (Driven by System) Valid Write Data (Driven by LSI53C896) MAS1/ (Driven by LSI53C896) MAS0/ (Driven by LSI53C896) MCE/ (Driven by LSI53C896) MOE/ (Driven by LSI53C896) MWE/ (Driven by LSI53C896)
Page 318 TRDY/ (Driven by LSI53C896) STOP/ (Driven by LSI53C896) DEVSEL/ (Driven by LSI53C896) Middle High Order Order Order (Addr Driven by LSI53C896 Address Address Address Data Driven by Memory) MAS1/ (Driven by LSI53C896) MAS0/ (Driven by LSI53C896) MCE/ (Driven by LSI53C896)
Page 319 TRDY/ (Driven by LSI53C896) STOP/ (Driven by LSI53C896) DEVSEL/ (Driven by LSI53C896) Data In Low Order Data In (Addr Driven by LSI53C896 Address Data Driven by Memory) MAS1/ (Driven by LSI53C896) MAS0/ (Driven by LSI53C896) MCE/ (Driven by LSI53C896) MOE/...
Page 320 AD[31:0] Data (Driven by Master) C_BE[3:0]/ Byte (Driven by Master) Enable (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C896) STOP/ (Driven by LSI53C896) DEVSEL/ (Driven by LSI53C896) Middle Order High Order Order Data Out (Driven by LSI53C896)
Page 321 AD[31:0] Data In (Driven by Master) C_BE[3:0]/ Byte Enable (Driven by Master) (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C896) STOP/ (Driven by LSI53C896) DEVSEL/ (Driven by LSI53C896) Low Order Address Data Out (Driven by LSI53C896) MAS1/...
Page 322: Slow Memory (≥ 128 Kbytes) Read Cycle
Data setup to CLK HIGH – Figure 6.31 Slow Memory (≥ 128 Kbytes) Read Cycle (Driven by System) Middle Order High Order Low Order (Addr driven by LSI53C896 Address Address Address Data drvn by mem) MAS1/ (Driven by LSI53C896) MAS0/...
Page 323 Figure 6.31 Slow Memory (≥ 128 Kbytes) Read Cycle (Cont.) (Driven by System) Valid Read (Addr driven by LSI53C896; Data Data Driven by Memory) MAS1/ (Driven by LSI53C896) MAS0/ (Driven by LSI53C896) MCE/ (Driven by LSI53C896) MOE/ (Driven by LSI53C896)
Page 324 MWE/ HIGH to MCE/ HIGH – Figure 6.32 Slow Memory (≥ 128 Kbytes) Write Cycle (Driven by System) Valid Middle Order High Order Low Order Write (Driven by LSI53C896) Address Address Address Data MAS1/ (Driven by LSI53C896) MAS0/ (Driven by LSI53C896)
Page 325 Figure 6.32 Slow Memory (≥ 128 Kbytes) Write Cycle (Cont.) (Driven by System) Valid Write Data (Driven by LSI53C896) MAS1/ (Driven by LSI53C896) MAS0/ (Driven by LSI53C896) MCE/ (Driven by LSI53C896) MOE/ (Driven by LSI53C896) MWE/ (Driven by LSI53C896) PCI and External Memory Interface Timing Diagrams...
Page 326 Data setup to CLK HIGH – Figure 6.33 ≤ 64 Kbytes ROM Read Cycle (Driven by System) Valid High Order Read Low Order (Addr driven by LSI53C896; Data Address Address Data driven by Memory) MAS1/ (Driven by LSI53C896) MAS0/ (Driven by LSI53C896)
Page 327: Kbytes Rom Write Cycle
MWE/ HIGH to MCE/ HIGH – Figure 6.34 ≤ 64 Kbytes ROM Write Cycle (Driven by System) High Order Low Order Valid Write Data Address (Driven by LSI53C896) Address MAS1/ (Driven by LSI53C896) MAS0/ (Driven by LSI53C896) MCE/ (Driven by LSI53C896)
Page 328: Scsi Timing Diagrams
6.5 SCSI Timing Diagrams Tables 6.39 through 6.49 and Figures 6.35 through 6.40 and describe the LSI53C896 SCSI timing. Table 6.39 Initiator Asynchronous Send Symbol Parameter Units SACK/ asserted from SREQ/ asserted – SACK/ deasserted from SREQ/ deasserted – Data setup to SACK/ asserted –...
Page 329: Initiator Asynchronous Receive
Table 6.40 Initiator Asynchronous Receive Symbol Parameter Units SACK/ asserted from SREQ/ asserted – SACK/ deasserted from SREQ/ deasserted – Data setup to SREQ/ asserted – Data hold from SACK/ asserted – Figure 6.36 Initiator Asynchronous Receive SREQ/ n + 1 SACK/ n + 1 SD[15:0]/,...
Page 330: Target Asynchronous Receive
Table 6.42 Target Asynchronous Receive Symbol Parameter Units SREQ/ deasserted from SACK/ asserted – SREQ/ asserted from SACK/ deasserted – Data setup to SACK/ asserted – Data hold from SREQ/ deasserted – Figure 6.38 Target Asynchronous Receive SREQ/ n + 1 SACK/ n + 1 SD[15:0]/,...
Page 331 Table 6.43 SCSI-1 Transfers (SE 5.0 Mbytes) Symbol Parameter Units Send SREQ/ or SACK/ assertion pulse width – Send SREQ/ or SACK/ deassertion pulse width – Receive SREQ/ or SACK/ assertion pulse width – Receive SREQ/ or SACK/ deassertion pulse width –...
Page 332 Table 6.45 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes (16-Bit Transfers) 40 MHz Clock Symbol Parameter Units Send SREQ/ or SACK/ assertion pulse width – Send SREQ/ or SACK/ deassertion pulse width – Receive SREQ/ or SACK/ assertion pulse width –...
Page 333 Table 6.47 Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers) or 40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock Symbol Parameter Unit Send SREQ/ or SACK/ assertion pulse width – Send SREQ/ or SACK/ deassertion pulse width – Receive SREQ/ or SACK/ assertion pulse width –...
Page 334 Table 6.49 Ultra2 SCSI Transfers 40.0 Mbyte (8-Bit Transfers) or 80.0 Mbyte (16-Bit Transfers) Quadrupled 40 MHz Clock Symbol Parameter Unit Send SREQ/ or SACK/ assertion pulse width – Send SREQ/ or SACK/ deassertion pulse width – Receive SREQ/ or SACK/ assertion pulse width –...
Page 335: Package Drawings
6.6 Package Drawings The signal names are listed alphabetically, in Table 6.50, and numerically, in Table 6.51. The signal locations on the 329 Ball Grid Array (BGA) are illustrated in Figure 6.40. Figure 6.41 is the package drawing for the LSI53896. Package Drawings 6-67...
Page 336 Table 6.50 Signal Names and BGA Position Signal Signal Signal Signal Signal Name Name Name Name Name B_GPIO0_FETCH/AA14 C_BE3/ A_DIFFSENS B_GPIO1_ C_BE4/ A-GPIO0_ MASTER/ AC15 C_BE5/ FETCH/ AB16 B_GPIO2 AB15 C_BE6/ A_GPIO1_ B_GPIO3 AA15 C_BE7/ MASTER/Y16 B_GPIO4 AC16 A_GPIO2 AA16 B_SACK−...
Page 337 Table 6.51 Signal Names by BGA Position Signal Signal Signal Signal Signal Name Name Name Name Name MAD[4] AB20 A_SI_O+ B_SD3+ B_SACK2− MAD[1] AB21 A_SD9+ B_SD4+ DEVSEL/ AB22 A_SD11+ B_SD5− A_SD12+ STOP/ AB23 VDD-A C_BE3/ A_SD13+ BSERR/ AD24 A_SD15+ PERR/ AD26 A_SD0+ B_SMSG−...
Page 338: Lsi53C896 329 Bga (Bottom View)
Figure 6.40 LSI53C896 329 BGA (Bottom View) 6-70 Speciﬁcations...
Page 339: Lsi53C896 329 Bga Mechanical Drawing
Figure 6.41 LSI53C896 329 BGA Mechanical Drawing Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code VW. Package Drawings...
Page 340 6-72 Speciﬁcations...
Page 341: Register Summary
Device ID 0x02–0x03 Read Only Expansion ROM Base Address 0x30–0x33 Read/Write 4-12 Header Type 0x0E Read Only Interrupt Line 0x3C Read/Write 4-14 Interrupt Pin 0x3D Read Only 4-14 Latency Timer 0x0D Read/Write LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller...
Page 342 Table A.1 LSI53C896 Register Map (Cont.) Register Name Address Read/Write Page Max_Lat 0x3F Read Only 4-15 Min_Gnt 0x3E Read Only 4-15 Next Item Pointer 0x41 Read Only 4-16 Not Supported 0x0F – Not Supported 0x24–0x27 – 4-10 Power Management Capabilities (PMC) 0x42–0x43...
Page 343 Table A.1 LSI53C896 Register Map (Cont.) Register Name Address Read/Write Page Chip Type (CTYPE) 0x46 Read Only 4-85 Cumulative SCSI Byte Count (CSBC) 0xDC–0xDF Read/Write 4-115 Data Structure Address (DSA) 0x10–0x13 Read/Write 4-49 DMA Byte Counter (DBC) 0x24–0x26 Read/Write 4-65...
Page 344 Table A.1 LSI53C896 Register Map (Cont.) Register Name Address Read/Write Page Memory Move Write Selector (MMWS) 0xA4–0xA7 Read/Write 4-108 Phase Mismatch Jump Address 1 (PMJAD1) 0xC0–0xC3 Read/Write 4-111 Phase Mismatch Jump Address 2 (PMJAD2) 0xC4–0xC7 Read/Write 4-111 Remaining Byte Count (RBC) 0xC8–0xCB...
Page 345 Table A.1 LSI53C896 Register Map (Cont.) Register Name Address Read/Write Page SCSI First Byte Received (SFBR) 0x08 Read/Write 4-38 SCSI Input Data Latch (SIDL) 0x50–0x51 Read Only 4-99 SCSI Interrupt Enable One (SIEN1) 0x41 Read/Write 4-78 SCSI Interrupt Enable Zero (SIEN0)
Page 346 Register Summary...
Page 347: External Memory Interface Diagram Examples
D[7:0] LSI53C896 Q[7:0] HCT374 MAS0/ Q[5:0] D[5:0] HCT374 MAS1/ Note: MAD[3:1] pulled LOW internally. MAD bus sense logic enabled for 16 Kbyte of slow memory (200 ns devices @ 33 MHz). LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller...
Page 348: Kbyte Interface With 150 Ns Memory
D[7:0] MAD[7:0] A[7:0] 27C512-15/ A[15:8] MAD2 4.7 K 28F512-15/ Socket LSI53C896 D[7:0] Q[7:0] HCT374 MAS0/ Q[5:0] D[5:0] HCT374 MAS1/ Note: MAD 3, 1, 0 pulled LOW internally. MAD bus sense logic enabled for 64 Kbyte of fast memory (150 ns devices @ 33 MHz).
Page 349: Kbyte Or 1 Mbyte Interface With 150 Ns Memory
MWE/ MOE/ MCE/ D[7:0] MAD[7:0] A[7:0] 27C020-15/ A[15:8] MAD3 4.7 K 28F020-15/ Socket A[19:16] LSI53C896 D[7:0] Q[7:0] HCT374 MAS0/ Q[5:0] D[5:0] HCT374 MAS1/ MAD[3:0] Q[3:0] D[3:0] HCT377 Note: MAD[2:0] pulled LOW internally. MAD bus sense logic enabled for 128, 256, 512 Kbytes, or 1 Mbyte of fast memory (150 ns devices @ 33 MHz).
Page 350: Kbyte Interface With 150 Ns Memory
D[7:0] D[7:0] D[7:0] D[7:0] D[7:0] MAD[7:0] A[7:0] MAD3 4.7 K A[15:8] MAD1 4.7 K MAD3 4.7 K LSI53C896 D[7:0] Q[7:0] HCT374 MAS0/ Q[7:0] D[7:0] HCT374 MAS1/ MAD[2:0] D[2:0] MCE/ HCT377 HCT139 Note: MAD[2] pulled LOW internally. MAD bus sense logic enabled for 512 Kbytes of slow memory (150 ns devices, additional time required for HCT139 @ 33 MHz).
Page 351 (CON) 4-25, 4-51 (EN64DBMV) 4-104 (CP) 4-13 (EN64TIBMV) 4-104 (CSBC) 4-115 (ENC[3:0]) 4-32, 4-37 (CSF) 2-48, 4-98 (ENID) 4-40 (CTEST0) 4-55 (ENNDJ) 4-102 (CTEST1) 4-55 (ENPMJ) 4-101 (CTEST2) 4-56 (EPC) 4-23 LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller IX-1...
Page 352 (EPER) (MPEE) 4-61 (ERBA) 4-12 (MSG) 4-39, 4-41, 4-47 (ERL) 4-70 (NC) (ERMP) 4-70 (NIP) 4-16 (ESA) 4-114 (OLF) 4-44 (EWS) 4-30 (OLF1) 4-48 (EXC) 4-24 (ORF) 4-44 (EXT) 4-96 (ORF1) 4-47 (FBL[2:0]) 4-62 (PAR) 4-77, 4-81 (FBL3) 4-61 (PCICIE) 4-56 (FE) 4-86...
Page 353 (SI) 4-53 (WRIE) 4-59 (SID) 4-12 (WSR) 4-29 (SIEN0) 4-76 (WSS) 4-28 (SIEN1) 4-78 (ZMOD) 4-103 (SIGP) 4-50, 4-56 (ZSD) 4-61 (SIP) 4-52 Numerics (SIR) 4-42, 4-71 (SIST0) 4-79 16-bit system (S16) 4-98 (SIST1) 4-82 32/64-bit jump 5-31 (SLB) 4-95 32-bit addressing (SLPAR) 4-83...
Page 354 assert burst write even SCSI parity (force bad parity) (AESP) 4-25 32-bits address and data 6-34 SATN/ on parity error (AAP) 4-23 64-bits address and data 6-36 SCSI ACK/ signal (ACK) 4-39, 4-40 command and byte enables ATN/ signal (ATN) 4-39, 4-40 fault (BF) 4-42, 4-71...
Page 355 configured interrupt 2-45, 2-46, 2-48 as I/O (CIO) 4-56 enable (DIEN) 2-28, 2-45, 2-46, 4-71 as memory (CM) 4-56 interrupt pending (DIP) 4-52 connected (CON) 4-25, 4-51 interrupts 2-48 cumulative SCSI byte count (CSBC) 4-115 mode (DMODE) 2-7, 2-8, 2-9, 2-12, 2-25, 4-68 current next address (DNAD)
Page 356 space write command IDSEL 2-3, fetch signal enable (FE) 4-86 illegal instruction detected (IID) 4-42, 4-71 pin mode (FM) 4-58 immediate FIFO arbitration (IARB) 4-26 byte control (FBL[2:0]) 4-62 data 5-24 byte control (FBL3) 4-61 indirect addressing flags (FF[3:0]) 4-45 initialization device select flags, bit 4 (FF4) 4-48...
Page 357 2-10 receiver SCSI signals MWE/ 3-19 SCSI LVDlink 1-1, benefits operation 2-35 new capabilities (NC) new features in the LSI53C896 next item pointer register 4-16 Next_Item_Ptr (NIP) 4-16 no download mode 2-59 2-57 no flush 5-35 bus programming...
Page 358 normal/fast memory ( 128 Kbytes) (Cont.) power single byte access read cycle 6-46 and ground signals 3-21 single byte access write cycle 6-48 management 2-59 capabilities 4-16 control/status 4-17 state (PWS[1:0]) 4-18 opcode 5-10, 5-15, 5-23, 5-27 state D0 2-60 fetch burst capability 2-25 state D1...
Page 359 interrupt status zero (SIST0) 2-28, 2-44, 2-45, 2-47, 2-49, 4-79 interrupts 2-48 SACK 2-48 isolation mode (ISO) 4-93 SACs 2-22 longitudinal parity (SLPAR) 4-83 SCLK 3-13 loopback mode (SLB) 2-27, 4-95 quadrupler enable (QEN) 4-93 low level mode (LOW) 4-96 quadrupler select (QSEL) 4-94 LVDlink...
Page 360 select (Cont.) subsystem ID 2-59 instruction 5-17 (SID) 4-12 with ATN/ 5-21 subsystem vendor ID 2-59 with SATN/ on a start sequence (WATN) 4-23 (SVID) 4-11 selected (SEL) 2-46, 4-76, 4-80 SWIDE register 2-54 selection or reselection time-out (STO) 4-78, 4-82 SYNC_IRQD (SI) 4-53...
Page 361 Ultra SCSI (Cont.) enable (USE) 4-29 high voltage differential transfers 20.0 Mbytes (8-bit transfers) 80 MHz clock 6-65 40.0 Mbytes (16-bit transfers) 80 MHz clock 6-65 single-ended transfers 20.0 Mbytes (8-bit transfers) quadrupled 40 MHz clock 6-65 40.0 Mbytes (16-bit transfers) quadrupled 40 MHz clock 6-65 Ultra2 SCSI...
Page 362 IX-12 Index...
Page 363: Customer Feedback
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