Address And Data Signals - LSI LSI53C876 Technical Manual

3.1.2 Address and Data Signals

Table 3.2 Address and Data Signals
Name Pin No.
AD[31:0] 202, 203, 205,
207, 208, 1, 3, 4,
8, 10, 11, 12, 14,
16, 17, 18, 36,
37, 38, 40, 42,
43, 44, 46, 49,
50, 52, 53, 54,
56, 58, 59
B4, A3, C4, B2,
A2, B1, D2, C1,
E1, F2, F1, G3,
G1, H2, H1, J4,
P1, P2, R1, R2,
P4, R3, T2, T3,
V2, W1, Y1, W3,
Y2, V4, Y3, Y4
C_BE/[3:0] 5, 20, 34, 48
D1, J2, N2, V1
PAR 33, N1
Table 3.2 describes the signals for the Address and Data Signals group.
Type Strength Description
T/S 16 mA
PCI
T/S 16 mA
PCI
T/S 16 mA
PCI
PCI Interface Signals
Physical Dword Address and Data are
multiplexed on the same PCI pins. During the first
clock of a transaction, AD[31:0] contain a physical
byte address. During subsequent clocks, AD[31:0]
contain data. A bus transaction consists of an
address phase followed by one or more data
phases. PCI supports both read and write bursts.
AD[7:0] define the least significant byte, and
AD[31:24] define the most significant byte.
Bus Command and Byte Enables are multiplexed
on the same PCI pins. During the address phase
of a transaction, C_BE/[3:0] define the bus
command. During the data phase, C_BE/[3:0] are
used as byte enables. The byte enables determine
which byte lanes carry meaningful data. C_BE/[0]
applies to byte 0, and C_BE/[3] to byte 3.
Parity is the even parity bit that protects the
AD[31:0] and C_BE/[3:0] lines. During address
phase, both the address and command bits are
covered. During data phase, both data and byte
enables are covered.
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