LSI LSI53C876 Technical Manual

Pci to dual channel scsi multifunction controller

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TECHNICAL

MANUAL

LSI53C876/876E

PCI to Dual Channel

SCSI Multifunction

Controller

Version 2.1

M a r c h 2 0 0 1

S14066

Table of Contents

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Summary of Contents for LSI LSI53C876

Page 1 TECHNICAL MANUAL LSI53C876/876E PCI to Dual Channel SCSI Multifunction Controller Version 2.1 M a r c h 2 0 0 1 ® S14066...
Page 2 LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties.
Page 3 Preface This book is the primary reference and technical manual for the LSI Logic LSI53C876/876E PCI to Dual Channel SCSI Multifunction Controller. It contains a complete functional description for the product and includes complete physical and electrical speciﬁcations. This technical manual assumes the user is familiar with the current and proposed standards for SCSI and PCI.
Page 4 Document names: SCSI Bench Reference, SCSI Encyclopedia, SCSI Tutor Prentice Hall 113 Sylvan Avenue Englewood Cliffs, NJ 07632 (800) 947-7700 Ask for document number ISBN 0-13-796855-8, SCSI: Understanding the Small Computer System Interface LSI Logic World Wide Web Home Page www.lsil.com Preface...
Page 5 Hexadecimal numbers are indicated by the preﬁx “0x” —for example, 0x32CF. Binary numbers are indicated by the preﬁx “0b” —for example, 0b0011.0010.1100.1111. Revision Record Revision Date Remarks 9/96 Prelimiary technical manual. 11/97 Revised technical manual. 3/01 All product names changed from SYM to LSI. Preface...
Page 6 Preface...
Page 7: Table Of Contents
Contents Chapter 1 General Description Wide Ultra SCSI Beneﬁts ® TolerANT Technology LSI53C876 Beneﬁts 1.3.1 PCI Performance 1.3.2 SCSI Performance 1.3.3 Testability 1.3.4 Integration 1.3.5 Reliability Chapter 2 Functional Description PCI Functional Description 2.1.1 PCI Addressing 2.1.2 PCI Bus Commands and Functions Supported 2.1.3...
Page 8 Serial EEPROM Interface 2-45 2.4.1 Mode A Operation 2-45 2.4.2 Mode B Operation 2-46 2.4.3 Mode C Operation 2-46 2.4.4 Mode D Operation 2-48 Power Management 2-48 2.5.1 Power State D0 2-49 2.5.2 Power State D1 2-49 2.5.3 Power State D2 2-49 2.5.4 Power State D3...
Page 9 Block Move Instruction 5.3.1 First Dword 5.3.2 Second Dword 5-13 I/O Instruction 5-13 5.4.1 First Dword 5-13 5.4.2 Second Dword 5-22 Read/Write Instructions 5-22 5.5.1 First Dword 5-22 5.5.2 Second Dword 5-24 5.5.3 Read-Modify-Write Cycles 5-24 5.5.4 Move To/From SFBR Cycles 5-25 Transfer Control Instructions 5-27...
Page 10 Figures Typical LSI53C876 System Application Typical LSI53C876 Board Application LSI53C876 Block Diagram Parity Checking/Generation 2-20 DMA FIFO Sections 2-20 LSI53C876 Host Interface SCSI Data Paths 2-24 LSI53C876 Differential Wiring Diagram 2-27 Regulated Termination 2-29 Determining the Synchronous Transfer Rate 2-32...
Page 11 6.12 Target Write (Not From External Memory) 6-20 6.13 Target Read, from External Memory 6-22 6.14 Target Write, from External Memory 6-26 6.15 Opcode Fetch, Nonburst 6-29 6.16 Opcode Fetch, Burst 6-31 6.17 Back-to-Back Read 6-33 6.18 Back-to-Back Write 6-35 6.19 Burst Read 6-38...
Page 12 Power and Ground Signals 3-20 3.17 Decode of MAD Pins 3-22 PCI to SCSI Conﬁguration Register Map LSI53C876 SCSI Register Address Map 4-21 Examples of Synchronous Transfer Periods for SCSI-1 Transfer Rates 4-35 Example Transfer Periods for Fast SCSI and Wide Ultra...
Page 13: Target Write (Not From External Memory)
Input Signals—CLK, SCLK, GNT/, IDSEL, RST/, TESTIN, DIFFSENS Capacitance Output Signals—INTA/, INTB/ Output Signals—SDIR[15:0], SDIRP0, SDIRP1, BSYDIR, SELDIR, RSTDIR, TGS, IGS, MAS/[1:0], MCE/, MOE/_TESTOUT, MWE/ Output Signal—REQ/ 6.10 Output Signal—SERR/ 6.11 Bidirectional Signals—AD[31:0], C_BE/[3:0], FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR 6.12 Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/, GPIO2, GPIO3, GPIO4...
Page 14: Write Cycle, Slow Memory (≥ 128 Kbytes)
Read Cycle, Slow Memory (≥ 128 Kbytes) 6-50 6.40 Write Cycle, Slow Memory (≥ 128 Kbytes) 6-51 6.41 Write Cycle, 16 Kbytes ROM 6-53 6.42 LSI53C876 PCI and External Memory Interface Timing 6-54 6.43 Initiator Asynchronous Send 6-55 6.44 Initiator Asynchronous Receive 6-56 6.45...
Page 15: Chapter 1 General Description
Grid Array (BGA) provides a differential SE interface on both SCSI Function A and SCSI Function B. The LSI53C876 has a local memory bus for storage of the device’s BIOS ROM in Flash memory or standard EPROMs. The LSI53C876 supports programming of local Flash memory for updates to BIOS or SCRIPTS™...
Page 16: Typical Lsi53C876 System Application
The LSI53C876 reduces the requirement for system BIOS support and PCI bus bandwidth. It also supports the Wide Ultra SCSI standard. The LSI53C876 performs Wide Ultra SCSI transfers or Fast SCSI transfers, and it improves performance by optimizing PCI bus utilization.
Page 17: Typical Lsi53C876 Board Application
PCI Address, Data, Parity and Control Signals The LSI53C876 integrates a high-performance SCSI core, a PCI bus master DMA core, and the LSI Logic SCSI SCRIPTS processor to meet the ﬂexibility requirements of SCSI, Fast SCSI, and Wide Ultra SCSI standards.
Page 18: Wide Ultra Scsi Beneﬁts
SCSI operations. TolerANT input signal ﬁltering is a built in feature of the LSI53C876 and all LSI Logic Fast SCSI and Ultra SCSI devices. The beneﬁts of TolerANT technology include increased immunity to noise on the deasserting signal edge, better performance due to balanced duty cycles, and improved Fast SCSI transfer rates.
Page 19: Lsi53C876 Beneﬁts
TolerANT technology is compatible with both the Alternative One and Alternative Two termination schemes proposed by the American National Standards Institute (ANSI). 1.3 LSI53C876 Beneﬁts This section provides an overview of the LSI53C876 features and beneﬁts. It contains information on Performance, SCSI Performance, Testability, Integration, and Reliability.
Page 20: Testability
Compatible with LSI53C875 software (drivers and SCRIPTS). • Enables Ultra SCSI with 40 MHz SCSI clock input with integrated clock doubler. 1.3.3 Testability The LSI53C876 contains these testability features: • All SCSI signals accessible through programmed I/O. • SCSI loopback diagnostics.
Page 21: Integration
1.3.4 Integration The LSI53C876 contains these integration features: • Dual channel SCSI multifunction controller. • 3.3 V/5 V PCI interface. • Full 32-bit PCI DMA bus master. • Memory-to-Memory Move instructions allow use as a third-party PCI bus DMA controller.
Page 22 General Description...
Page 23: Chapter 2 Functional Description
Section 2.2, “SCSI Functional Description” • Section 2.3, “Parallel ROM Interface” • Section 2.4, “Serial EEPROM Interface” • Section 2.5, “Power Management” The LSI53C876 is a multifunction device composed of the following modules: • PCI Interface • Two independent PCI-to-Wide Ultra SCSI Controllers •...
Page 24 Figure 2.1 LSI53C876 Block Diagram PCI Bus PCI Master and Slave Control Block, PCI Conﬁguration Registers (2 sets), and SCSI Function Arbitration Wide Ultra SCSI Controller Wide Ultra SCSI Controller 8 Dword SCRIPTS 8 Dword SCRIPTS 4 Kbyte 4 Kbyte...
Page 25: Pci Functional Description
A conﬁguration read/write cycle without IDSEL is ignored. The eight lower order address bits AD[7:0], are used to select a speciﬁc 8-bit register. Since the LSI53C876 is a PCI multifunction device, AD[10:8] decodes either SCSI Function A Conﬁguration register (AD [10:8] = 000 binary) or SCSI Function B...
Page 26: Pci Bus Commands And Functions Supported
256-byte I/O area this device occupies. Memory Space – The PCI speciﬁcation deﬁnes memory space as a contiguous 32-bit memory address that is shared by all system resources, including the LSI53C876. The Base Address Register One (Memory) register determines which 256-byte memory area this device occupies.
Page 27 Chip Test Three (CTEST3) register. 2.1.2.1 Interrupt Acknowledge Command The LSI53C876 does not respond to this command as a slave and it never generates this command as a master. 2.1.2.2 Special Cycle Command The LSI53C876 does not respond to this command as a slave and it never generates this command as a master.
Page 28 This command is identical to the Memory Read command except that it additionally indicates that the master may intend to fetch more than one cache line before disconnecting. The LSI53C876 supports PCI Read Multiple functionality and issues Read Multiple commands on the PCI...
Page 29 Chip Test Five (CTEST5), bit 2. 2.1.2.11 Dual Address Cycles (DACs) Command The LSI53C876 does not respond to this command as a slave, and it never generates this command as a master. 2.1.2.12 Memory Read Line Command This command is identical to the Memory Read command, except that it additionally indicates that the master intends to fetch a complete cache line.
Page 30 Line bit (DMA Mode (DMODE) register, bit 3) is modiﬁed to more resemble the Write and Invalidate mode in terms of conditions that must be met before a Read Line command is issued. However, the Read Line option operates exactly like the previous LSI53C8XX chips when cache mode is disabled by a CLSE bit reset or when certain conditions exist in the chip (explained below).
Page 31 • The chip is aligned to a cache line boundary. When these conditions are met, the LSI53C876 issues a Write and Invalidate command instead of a Memory Write command during all PCI write cycles. Multiple Cache Line Transfers – The Write and Invalidate command can write multiple cache lines of data in a single bus ownership.
Page 32: Internal Arbiter
2.1.3 Internal Arbiter The PCI to SCSI controller uses a single REQ/ - GNT/ signal pair to arbitrate for access to the PCI bus. The LSI53C876 uses a round robin arbitration scheme to allow both SCSI functions to arbitrate for PCI bus access.
Page 33: Pci Cache Mode
2.1.4.2 Alignment The LSI53C876 uses the calculated line size value to monitor the current address for alignment to the cache line size. When it is not aligned, the chip attempts to align to the cache boundary by using a “smart aligning”...
Page 34 Alignment stops, and the burst size from then on is switched to 16. 2.1.4.3 Memory Move Misalignment The LSI53C876 does not operate in a cache alignment mode when a Memory Move instruction type is issued and the read and write addresses are different distances from the nearest cache line boundary.
Page 35: Scsi Functional Description
2.2 SCSI Functional Description 2.2.1 Two SCSI Controllers The LSI53C876 provides two SCSI controllers on a single chip. Each SCSI controller provides a SCSI function that supports an 8-bit or 16-bit bus. Each supports Ultra SCSI synchronous transfer rates up to 40 Mbytes/s, Ultra SCSI synchronous transfer rates up to 20 Mbytes/s, and asynchronous transfer rates up to 14 Mbytes/s on a wide SCSI bus.
Page 36 2.2.2.1 Internal SCRIPTS RAM The LSI53C876 has 4 Kbytes (1024 x 32 bits) of internal, general purpose RAM. The RAM is designed for SCRIPTS program storage, but is not limited to this type of information. When the chip fetches SCRIPTS instructions or Table Indirect information from the internal RAM, these fetches remain internal to the chip and do not use the PCI bus.
Page 37 SCRIPTS RAM, prefetching is not necessary when fetching instructions from this memory. The LSI53C876 may ﬂush the contents of the prefetch unit under certain conditions, listed below, to ensure that the chip always operates from the most current version of the SCRIPTS instruction. When one of these conditions apply, the contents of the prefetch unit are automatically ﬂushed.
Page 38: Jtag Boundary Scan Testing
CLAMP, HIGH-Z, and IDCODE instructions. The LSI53C876 uses an 8-bit instruction register to support all boundary scan instructions. The data registers included in the device are the Boundary Data register, the IDCODE register, and the Bypass register.
Page 39: Scsi Loopback Mode
SCSI Test Two (STEST2) register, bit 4, the LSI53C876 allows control of all SCSI signals, whether the chip is operating in the initiator or target mode. For more information on this mode of operation, refer to the SCSI SCRIPTS Processors Programming Guide .
Page 40 Enables parity checking during master data phases. Enable (CTEST4), Bit 3 Master Data Parity Error DMA Status Set when the LSI53C876, as a PCI master, detects a (DSTAT), Bit 6 target device signaling a parity error during a data phase. Master Data Parity Error...
Page 41 Table 2.3 SCSI Parity Control AESP Description Does not check for parity errors. Parity is generated when sending SCSI data. Asserts odd parity when sending SCSI data. Does not check for parity errors. Parity is generated when sending SCSI data. Asserts even parity when sending SCSI data. Checks for odd parity on SCSI data received.
Page 42: Dma Fifo
Figure 2.2 Parity Checking/Generation Asynchronous Synchronous Synchronous Asynchronous SCSI Send SCSI Send SCSI Receive SCSI Receive PCI Interface** PCI Interface** PCI Interface** PCI Interface** DMA FIFO* DMA FIFO* DMA FIFO* DMA FIFO* (32 Bits x 134) (32 Bits x 134) (32 Bits x 134) (32 Bits x 134) SCSI FIFO*...
Page 43 The LSI53C876 automatically supports misaligned DMA transfers. A 536-byte FIFO allows the LSI53C876 to support 2, 4, 8, 16, 32, 64, or 128 Dword bursts across the PCI bus interface. 2.2.6.1 Data Paths The data path through the LSI53C876 depends on whether data is being moved into or out of the chip, and whether SCSI data is being transferred asynchronously or synchronously.
Page 44 Synchronous SCSI Send – Step 1. If the DMA FIFO size is set to 88 bytes, look at the DMA FIFO (DFIFO) DMA Byte Counter (DBC) registers and calculate if there are bytes left in the DMA FIFO. To make this calculation, subtract the seven least signiﬁcant bits of the DMA Byte Counter (DBC)
Page 45 If the DMA FIFO size is set to 536 bytes (bit 5 of the Chip Test Five (CTEST5) register is set), subtract the 10 least signiﬁcant bits of the DMA Byte Counter (DBC) register from the 10-bit value of the DMA FIFO Byte Offset Counter, which consists of bits [1:0] in the Chip Test Five (CTEST5) register and bits [7:0]...
Page 46: Scsi Bus Interface
SCSI Interface 2.2.7 SCSI Bus Interface All SCSI signals are active LOW. The LSI53C876 contains the SE output drivers and can be connected directly to the SCSI bus. Each output is isolated from the power supply to ensure that a powered-down LSI53C876 has no effect on an active SCSI bus (CMOS “voltage...
Page 47 MSG/, C/D/, I/O/, and REQ/. DIFFSENS Input to the LSI53C876 used to detect the presence of an SE device on a differential system. If a logical zero is detected on this pin, then it is assumed that an SE device is on the bus and all SCSI outputs will be 3-stated to avoid damage to the transceiver.
Page 48 Ultra SCSI transfer rates. 8-Bit/16-Bit SCSI and the Differential Interface – In an 8-bit SCSI bus, the SD[15:8] pins on the LSI53C876 should be pulled up with a 1.5 kΩ. resistor or terminated like the rest of the SCSI bus lines. This is very important, as errors may occur during reselection if these lines are left ﬂoating.
Page 49: Lsi53C876 Differential Wiring Diagram
Figure 2.5 LSI53C876 Differential Wiring Diagram DIFFSENS Schottky DIFFSENS (pin 21) Diode 1.5 K SN75976A #1 LSI538760 CDE0 CDE1 SELDIR -SEL (42) CDE2 BSYDIR +SEL (41) RSTDIR -BSY (34) +BSY (33) SEL/ SEL/ -RST (38) 1.5 KΩ BSY/ SELDIR +RST (37)
Page 50 SE cables can use a 220 Ω pull-up to the terminator power supply (Term Power) line and a 330 Ω pull-down to ground. Because of the high-performance nature of the LSI53C876, regulated (or active) termination is recommended. Figure 2.6 shows a Unitrode active terminator.
Page 51 Note: If the LSI53C876 is to be used in a design with only an 8-bit SCSI bus, all 16 data lines must still be terminated or pulled high. Active termination is required for Wide Ultra SCSI synchronous transfers. Figure 2.6...
Page 52: Synchronous Operation
SCRIPTS execution begins, from within SCRIPTS using a Table Indirect I/O instruction, or with a Read-Modify-Write instruction. The LSI53C876 can receive data from the SCSI bus at a synchronous transfer period as short as 50 ns, regardless of the transfer period used to send data.
Page 53 50 ns, which is half the 100 ns period allowed under Fast SCSI. This allows a maximum transfer rate of 40 Mbytes/s on a 16-bit SCSI bus. The LSI53C876 requires that the 40 MHz clock is doubled by the internal clock doubler (see the SCSI Test One (STEST1) register description) to perform Wide Ultra SCSI transfers.
Page 54: Designing A Wide Ultra Scsi System
Figure 2.7 Determining the Synchronous Transfer Rate SCF2 SCF1 SCF0 XFERP Divisor Divisor This point must not Synchronous Send Divider exceed Clock 80 MHz SCSI Bus Receive Divide by 4 Divider Clock SCLK 40 MHz Doubler Asynchronous Divider SCSI Logic This point must not exceed...
Page 55: Interrupt Handling
A hybrid approach would use hardware interrupts for long waits, and use polling for short waits. 2.2.10.2 Registers The registers in the LSI53C876 that are used for detecting or deﬁning interrupts are the Interrupt Status (ISTAT),...
Page 56 Reading these registers determines which condition or conditions caused the SCSI-type interrupt, and clears that SCSI interrupt condition. If the LSI53C876 is receiving data from the SCSI bus and a fatal interrupt condition occurs, the chip attempts to send the contents of the DMA FIFO to memory before generating the interrupt.
Page 57 SCSI Interrupt Status Zero (SIST0) SCSI Interrupt Status One (SIST1) being set) are nonfatal. When the LSI53C876 is operating in the Initiator mode, only the Function Complete (CMP), Selected (SEL), Reselected (RSL), General Purpose Timer Expired (GEN), and Handshake-to-Handshake Timer Expired (HTH) interrupts are nonfatal.
Page 58 CPU. This prevents an interrupt when arbitration is complete (CMP set), when the LSI53C876 is selected or reselected (SEL or RSL set), when the initiator asserts ATN (target mode: SATN/ active), or when the General Purpose or Handshake-to-Handshake timers expire.
Page 59 Masking an interrupt after INTA/ (or INTB/) is asserted does not cause deassertion of INTA/ (or INTB/). 2.2.10.5 Stacked Interrupts The LSI53C876 stacks interrupts if they occur one after the other. If the SIP or DIP bits in the Interrupt Status (ISTAT) register are set (ﬁrst level),...
Page 60 These “locked out” SCSI interrupts are posted as soon as the DMA FIFO is empty. 2.2.10.6 Halting in an Orderly Fashion When an interrupt occurs, the LSI53C876 attempts to halt in an orderly fashion. • If the interrupt occurs in the middle of an instruction fetch, the fetch is completed, except in the case of a Bus Fault.
Page 61 2.2.10.7 Sample Interrupt Service Routine The following is a sample of an interrupt service routine for the LSI53C876. It can be repeated if polling is used, or should be called when the INTA/ (or INTB/) pin is asserted during hardware interrupts.
Page 62: Chained Block Moves
2.2.11 Chained Block Moves Since the LSI53C876 has the capability to transfer 16-bit wide SCSI data, a unique situation occurs when dealing with odd bytes. The chained move (CHMOV) SCRIPTS instruction along with the Wide SCSI Send (WSS) and Wide SCSI Receive (WSR) bits in the...
Page 63 2.2.11.1 Wide SCSI Send Bit The WSS bit is set whenever the SCSI controller is sending data (Data-Out for initiator or Data-In for target), and the controller detects a partial transfer at the end of a chained Block Move SCRIPTS instruction (this ﬂag is not set if a normal Block Move instruction is used).
Page 64 stored data may be a residue byte (and therefore ignored) or it may be valid data that is transferred to memory at the beginning of the next Block Move instruction. 2.2.11.4 SODL Register For send data, the low-order byte of the SCSI Output Data Latch (SODL) register holds the low-order byte of a partial memory transfer which has not yet been transferred across the SCSI bus.
Page 65: Parallel Rom Interface
(Nth – 1) Block Move instructions should be Chained Block Moves. 2.3 Parallel ROM Interface The LSI53C876 supports up to one megabyte of external memory in binary increments from 16 Kbytes, to allow the use of expansion ROM for add-in PCI cards. Both functions of the device share the ROM interface.
Page 66 Appendix B, “External Memory Interface Diagram Examples.” The LSI53C876 supports a variety of sizes and speeds of expansion ROM, using pull-down resistors on the MAD[3:0] pins. The encoding of pins MAD[3:1] allows the user to deﬁne how much external memory is available to the LSI53C876.
Page 67: Serial Eeprom Interface
The LSI53C876 allows the system to determine the size of the available external memory using the Expansion ROM Base Address register in PCI conﬁguration space. For more information on how this works, refer to the PCI speciﬁcation or the Expansion ROM Base Address...
Page 68: Mode B Operation
Table 2.7 Mode A Serial EEPROM Data Format Byte Name Description 0x00 SVID(0) Subsystem Vendor ID, LSB. This byte is loaded into the least signiﬁcant byte of the Subsystem Vendor ID register in the appropriate PCI conﬁguration space at chip power-up or hard reset. 0x01 SVID(1) Subsystem Vendor...
Page 69 Subsystem ID Subsystem Vendor ID registers are read only, in accordance with the PCI speciﬁcation, with a default value of all zeros. Before implementing Mode C, contact LSI Logic for additional information. Table 2.8 Mode C Serial EEPROM Data Format...
Page 70: Mode D Operation
2.4.4 Mode D Operation No pull-down on MAD6, and a 4.7 K pull-down on MAD7. The Subsystem ID and the Subsystem Vendor ID are automatically set to 0x1000. This allows the OEM to have a non-zero value in the registers without requiring a serial EEPROM on the board.
Page 71: Power State D0
Power state D1 is a lower power state than D0. In this state, the LSI53C876 core is placed in the snooze mode and the SCSI CLK is disabled. In the snooze mode, a SCSI reset does not generate an /IRQ signal.
Page 72: Power State D3
Power state D3 is a lower power level than power state D2. In this state, the LSI53C876 core is placed in the coma mode. Furthermore, the function’s soft reset is continually asserted while in power state D3, which clears all pending interrupts and 3-states the SCSI bus.
Page 73: Chapter 3 Signal Descriptions
This chapter presents the LSI53C876 pin conﬁguration and signal deﬁnitions using tables and illustrations. Figure 3.1 Figure 3.2 the pin diagrams for all versions of the LSI53C876 and Figure 3.3 is the functional signal grouping. The pin deﬁnitions are presented in Table 3.1...
Page 74 Figure 3.1 LSI53C876 208-Pin PQFP Diagram A_S07/ AD26 A_SDP0/ AD25 A_SATN/ AD24 VSS-S C_BE3/ A_SBSY/ VDD-IO A_SACK/ A_SRST/ IDSEL A_SMSG/ AD23 A_SSEL/ VSS-S AD22 AD21 A_SC_0/ AD20 A_SREQ/ VDD-IO A_SI_0/ AD19 A_SD8/ VSS-S A_SD9/ AD18 A_SD10/ AD17 A_SD11/ AD16 C_BE2/...
Page 75: Lsi53C876 256-Ball Bga Diagram (Top View)
Figure 3.2 LSI53C876 256-Ball BGA Diagram (Top View) AD27 AD30 REQ/ RST/ MCE/ MWE/ B_IGS B_SDIR13 A_SDIR13 A_SDIR0 A_SDIR4 A_SDIR7 A_SD12/ A_SDP1/ A_SD2 A_SD3 A_SD6/ A_SD7/ AD26 AD28 VDD-IO AD31 GNT/ INTA/ MOE/_TO MAS1/ A_SDIR12 A_SDIR15 A_SDIR1 A_SDIR5 A_DIRP0/1 A_SD13/...
Page 76: Lsi53C876 Functional Signal Grouping
Figure 3.3 LSI53C876 Functional Signal Grouping LSI53C876 SCLK System A_SD[15:0]/ A_SDP[1:0]/ AD[31:0] A_SC_D/ Address C_BE/[3:0] A_SI_O/ and Data A_SMSG/ SCSI Function A A_SREQ/ SCSI Bus FRAME/ Interface A_SACK/ A_SCTRL/ TRDY/ A_SBSY/ Interface IRDY/ A_SATN/ Control STOP/ A_SRST/ DEVSEL/ A_SSEL/ IDSEL...
Page 77 The LSI53C876 signals are divided into three primary interfaces: • PCI Interface • SCSI Interface • ROM/Flash Memory Interface A slash (/) at the end of the signal name indicates that the active state occurs when the signal is at a LOW voltage. When the slash is absent, the signal is active at a HIGH voltage.
Page 78: Pci Interface Signals
3.1 PCI Interface Signals The PCI interface signals are organized into the following functional groups: System Signals, Address and Data Signals, Interface Control Signals, Arbitration Signals, Error Reporting Signals, PCI Interrupt Signals, and GPIO Interface Signals. 3.1.1 System Signals Table 3.1 describes the signals for the System Signals group.
Page 79: Address And Data Signals
3.1.2 Address and Data Signals Table 3.2 describes the signals for the Address and Data Signals group. Table 3.2 Address and Data Signals Name Pin No. Type Strength Description AD[31:0] 202, 203, 205, 16 mA Physical Dword Address and Data are 207, 208, 1, 3, 4, multiplexed on the same PCI pins.
Page 80: Interface Control Signals
3.1.3 Interface Control Signals Table 3.3 describes the signals for the Interface Control Signals group. Table 3.3 Interface Control Signals Name Pin No. Type Strength Description FRAME/ 21, J1 S/T/S 16 mA Cycle Frame is driven by the current master to indicate the beginning and duration of an access.
Page 81: Arbitration Signals
3.1.4 Arbitration Signals Table 3.4 describes the signals for the Arbitration Signals group. Table 3.4 Arbitration Signals Name Pin No. Type Strength Description REQ/ 200, A4 16 mA PCI Request indicates to the system arbiter that this agent desires use of the PCI bus. Both SCSI functions share the GNT/ signal.
Page 82: Pci Interrupt Signals
This interrupt can be rerouted at power-up using the INTA/ enable sense resistor (pull-down on MAD4). This causes the LSI53C876 to program the SCSI Function B PCI register Interrupt Pin (3D) to 0x01.
Page 83: Gpio Interface Signals
SCSI Function A General Purpose I/O pin 1. MASTER/ Optionally, when driven LOW, indicates that the LSI53C876 is bus master. This pin is programmable at power-up through the MAD[7:6] pins to serve as either the data or clock signal for the serial EEPROM interface.
Page 84 SCSI Function B General Purpose I/O pin 1. MASTER/ Optionally, when driven LOW, indicates that the LSI53C876 is bus master. This pin is programmable at power-up through the MAD[7:6] pins to serve as either the data or clock signal for the serial EEPROM interface.
Page 85: Scsi Bus Interface Signals
3.2 SCSI Bus Interface Signals The SCSI Bus Interface signals section contains tables describing the signals for the following signal groups: SCSI Bus Interface Signal SCSI Bus Interface. 3.2.1 SCSI Bus Interface Signal Table 3.9 describes the SCSI Bus Interface signal. Table 3.9 SCSI Bus Interface Signal Name...
Page 86: Scsi Bus Interface
3.2.2 SCSI Bus Interface Table 3.10 describes the signals for the SCSI Function A Signals group. Table 3.10 SCSI Function A Interface Signals Name Pin No. Type Strength Description A_SD[15:0]/, 167, 169, 170, 171, 48 mA SCSI Function A Data includes the following A_SDP[1:0]/ 139, 140, 141, 143, SCSI...
Page 87 Table 3.11 describes the signals for the SCSI Function B Signals group. Table 3.11 SCSI Function B Interface Signals Name Pin No. Type Strength Description B_SD/[15:0], 119, 121, 122, 123, 48 mA SCSI Function B Data includes the following B_SDP/[1:0] 91, 92, 93, 95, 108, SCSI data lines and parity signals: B_SD/[15:0]...
Page 88 Table 3.12 describes the signals for the SCSI Function A Differential Control Signals group. Table 3.12 SCSI Function A Differential Control Signals Name Pin No. Type Strength Description A_SDIR[15:0]/ 183, 184, 185, 187, 4 mA Driver direction control for SCSI Function A 134, 135, 136, 137, data lines.
Page 89 Table 3.13 describes the signals for the SCSI Function B Differential Control Signals group. Table 3.13 SCSI Function B Differential Control Signals Name Pin No. Type Strength Description B_SDIR[15:0]/ C10, D10, A9, C9, 4 mA Driver direction control for SCSI Function B W14, Y15, V14, data lines.
Page 90: Rom/Flash Interface Signals
3.3 ROM/Flash Interface Signals Table 3.14 describes the signals for the ROM/Flash Interface Signals group. Table 3.14 ROM/Flash Interface Signals Name Pin No. Type Strength Description MAS0/ 190, C8 4 mA Memory Address Strobe 0. This pin is used to latch in the least signiﬁcant address byte of an external EPROM or Flash memory.
Page 91: Test Interface Signals
Table 3.14 ROM/Flash Interface Signals (Cont.) Name Pin No. Type Strength Description MWE/ 191, A7 4 mA Memory Write Enable. This pin is used as a write enable signal to an external Flash memory. MOE/_TESTOUT 192, B7 4 mA Memory Output Enable. This pin is used as an output enable signal to an external EPROM or Flash memory during read operations.
Page 92: Power And Ground Signals
Table 3.15 Test Interface Signals (Cont.) 61, W5 Test Data In. Serial test instructions are received by the JTAG test logic at this pin. It has a static pull-up. 63, V6 Test Data Out. This pin is the serial output for test instructions and data from the JTAG test logic.
Page 93: Isolated Power Supplies
3.5.1 Isolated Power Supplies The I/O driver pad rows and digital core have isolated power supplies as delineated by the "I/O" and "CORE" extensions on their respective V and V names. These power and ground pins should be connected directly to the primary power and ground planes of the circuit board.
Page 94 Table 3.17 Decode of MAD Pins MAD[3:1] Available Memory Space 16 Kbytes 32 Kbytes 64 Kbytes 128 Kbytes 256 Kbytes 512 Kbytes 1024 Kbytes No external memory present • MAD[0] – The slow ROM pin. When pulled down, it enables two extra cycles of data access time to allow use of slower memory devices.
Page 95: Chapter 4 Registers
Chapter 4 Registers This chapter describes all LSI53C876 registers and is divided into the following sections: • Section 4.1, “PCI Conﬁguration Registers” • Section 4.2, “SCSI Registers” 4.1 PCI Conﬁguration Registers The PCI Conﬁguration registers are accessed by performing a conﬁguration read/write to the device with its IDSEL pin asserted and the...
Page 96 Table 4.1 PCI to SCSI Conﬁguration Register Map 16 15 Device ID Vendor ID 0x00 Status Command 0x04 Class Code Revision ID 0x08 Not Supported Header Type Latency Timer Cache Line Size 0x0C Base Address Register Zero (I/O) SCSI Operating Registers 0x10 Base Address Register One (Memory) bits [31:0] SCSI Operating Registers...
Page 97 The Command register provides coarse control over a device’s ability to generate and respond to PCI cycles. When a zero is written to this register, the LSI53C876 is logically disconnected from the PCI bus for all accesses except conﬁguration accesses.
Page 98 Power State D2. Reserved Write and Invalidate Enable This bit allows a SCSI function of the LSI53C876 to generate write and invalidate commands on the PCI bus. The WRIE bit in the Chip Test Three (CTEST3)
Page 99 15 and not affect any other bits, write the value 0x8000 to the register. Detected Parity Error (from Slave) This bit is set by the a SCSI function of the LSI53C876 whenever it detects a data parity error, even if data parity error handling is disabled.
Page 100 These bits are read only and should indicate the slowest time that a device asserts DEVSEL/ for any bus command except Conﬁguration Read and Conﬁguration Write. In the SCSI functions of the LSI53C876, 0b01 is supported. Data Parity Reported This bit is set when the following conditions are met: •...
Page 101 Register: 0x08 Revision ID Read Only Revision ID [7:0] This ﬁeld speciﬁes device and revision identiﬁers. The value of this register is 0x00110111 or 0x37. Register: 0x09 Class Code Read Only Class Code [23:0] This register is used to identify the generic function of the device.
Page 102 The Latency Timer register speciﬁes, in units of PCI bus clocks, the value of the Latency Timer for this PCI bus master. The SCSI functions of the LSI53C876 support this timer. All eight bits are writable, allowing latency values of 0–255 PCI clocks. Use the following equation to calculate an optimum latency value for the SCSI functions of the LSI53C876.
Page 103 BIST Read Only BIST Capable Start BIST Completion Code This register is used for control and status of BIST. Since the LSI53C876 does not support BIST, this register is read only and always returns a value of 0x00. BIST BIST Capable...
Page 104 Register: 0x14 Base Address Register One (Memory) Read/Write BAR1 BAR1 Base Address Register One [31:0] This register has bit zero hardwired to zero. For detailed information on the operation of this register, refer to the PCI speciﬁcation. This Base Address Register One (Memory) register maps SCSI operating registers into memory space.
Page 105 Register: 0x2C Subsystem Vendor ID Read Only SVID If EEPROM not enabled Mode A If EEPROM note enabled Mode D EEPROM value if EEPROM enabled SVID Subsystem Vendor ID [15:0] This register uniquely identiﬁes the vendor manufacturing the add-in board or subsystem where this PCI device resides.
Page 106 Register: 0x2E Subsystem ID Read Only If EEPROM not enabled Mode A If EEPROM note enabled Mode D EEPROM value if EEPROM enabled Subsystem ID [15:0] This register uniquely identiﬁes the add-in board or subsystem where this PCI device resides. It provides a mechanism for an add-in card vendor to distinguish its cards from one another even if the cards have the same PCI controller installed on them (and therefore the same...
Page 107 Expansion ROM Base Address register with all ones and then reading back the register. The SCSI functions of the LSI53C876 respond with zeros in all don’t care locations. The ones in the remaining bits represent the binary version of the external memory size.
Page 108 Register: 0x34 Capabilities Pointer Read Only Capabilities Pointer [7:0] This register provides an offset into the function’s PCI Conﬁguration Space for the location of the ﬁrst item in the capabilities linked list. Only the LSI53C876E sets this register to 0x40. Register: 0x3C Interrupt Line Read/Write...
Page 109 This register speciﬁes the desired settings for latency timer values. Min_Gnt speciﬁes how long a burst period the device needs. The value speciﬁed in these registers is in units of 0.25 microseconds. The LSI53C876 SCSI function sets this register to 0x11. PCI Conﬁguration Registers...
Page 110 Max_Lat speciﬁes how often the device needs to gain access to the PCI bus. The value speciﬁed in these registers is in units of 0.25 microseconds. The LSI53C876 SCSI function sets this register to 0x40. Register: 0x40 Capability ID...
Page 111 Register: 0x41 Next Item Pointer Read Only Next_Item_Ptr [7:0] This register describes the location of the next item in the function’s capability list. This register applies only to the LSI53C876E, which sets this register to a value of 0x00, indicating that power management is the last capability in the linked list of extended capabilities.
Page 112 Auxiliary Power Source Because the LSI53C876E does not provide a PME signal, this bit always returns a 0, indicating that no auxiliary power source is required to support the PME signal in the D3cold power management state. PMEC PME Clock This ﬁeld is always set to 00000b because the LSI53C876E does not provide a PME signal.
Page 113 Reserved [7:2] Power State [1:0] This two bit ﬁeld determines the current power state for the function and is used to set the function to a new power state. The deﬁnition of the ﬁeld values are: 0b00 0b01 Reserved 0b10 Reserved 0b11 D3 hot...
Page 114: Scsi Registers
The LSI53C876E returns 0x00 as the default value. 4.2 SCSI Registers This section contains descriptions of all LSI53C876 SCSI registers. Table 4.2, the register map, lists registers by operating and conﬁguration addresses. The terms “set” and “assert” refer to bits that are programmed to a binary one.
Page 115 Table 4.2 LSI53C876 SCSI Register Address Map 16 15 SCNTL3 SCNTL2 SCNTL1 SCNTL0 0x00 GPREG SDID SXFER SCID 0x04 SBCL SSID SOCL SFBR 0x08 SSTAT2 SSTAT1 SSTAT0 DSTAT 0x0C 0x10 Reserved ISTAT 0x14 CTEST3 CTEST2 CTEST1 CTEST0 0x18 TEMP 0x1C...
Page 116 Simple arbitration Reserved Reserved Full arbitration, selection/reselection Simple Arbitration The LSI53C876 waits for a bus free condition to occur. It asserts SBSY/ and its SCSI ID (contained in the SCSI Chip ID (SCID) register) onto the SCSI bus. If the SSEL/ signal is asserted by another SCSI...
Page 117 SCNTL1 register to verify that the LSI53C876 is not connected to the SCSI bus. WATN Select with SATN/ on a Start Sequence When this bit is set and the LSI53C876 SCSI function is in initiator mode, the SATN/ signal is asserted during SCSI Registers 4-23...
Page 118 SCSI target device. The SATN/ signal informs the target that the LSI53C876 SCSI function has a message to send. If a selection time-out occurs while attempting to select a target device, SATN/ is deasserted at the same time SSEL/ is deasserted. When this bit is cleared, the SATN/ signal is not asserted during selection.
Page 119 When this bit is set, the chip is a target device by default. When this bit is cleared, the LSI53C876 SCSI function is an initiator device by default. Note: Writing this bit while not connected may cause the loss of a selection or reselection due to the changing of target or initiator modes.
Page 120 This bit is automatically set any time the LSI53C876 SCSI function is connected to the SCSI bus as an initiator or as a target. It is set after the LSI53C876 SCSI function successfully completes arbitration or when it has responded to a bus initiated selection or reselection. This bit is also set after the chip wins simple arbitration when operating in low level mode.
Page 121 Arbitration is retried until won. At that point, the LSI53C876 SCSI function holds BSY and SEL asserted, and waits for a select or reselect sequence. The Immediate Arbitration bit is reset automatically when the selection or reselection sequence is completed, or times out.
Page 122 value written to the I/O bit in SCSI Output Control Latch (SOCL). This bit is self-clearing. Do not set it for low level operation. Note: Writing to this register while not connected may cause the loss of a selection/reselection by resetting the Connected bit.
Page 123 LSI53C876 SCSI function stores the last byte in the SCSI Wide Residue (SWIDE) register during a receive operation, or in the SCSI Output Data Latch (SODL) register during a send operation. This byte is combined with the ﬁrst byte from the subsequent transfer so that a wide transfer is completed.
Page 124 VUE1 Vendor Unique Enhancement, Bit 1 This bit disables the automatic byte count reload during Block Move instructions in the command phase. If this bit is cleared, the device reloads the Block Move byte count if the ﬁrst byte received is one of the standard group codes.
Page 125 Register: 0x03 SCSI Control Three (SCNTL3) Read/Write SCF[2:0] CCF[2:0] Ultra SCSI Enable Setting this bit enables Ultra SCSI synchronous transfers. The default value of this bit is 0. Set this bit only when the transfer rate exceeds 10 megatransfers/s. When this bit is set, the signal ﬁltering period for SREQ/ and SACK/ automatically changes to 15 ns, regardless of the value of the Extend REQ/ACK Filtering bit in the SCSI...
Page 126 SCSI Chip ID (SCID) Read/Write ENC[3:0] Reserved Enable Response to Reselection When this bit is set, the LSI53C876 SCSI function is enabled to respond to bus-initiated reselection at the chip ID in the Response ID Zero (RESPID0) Response ID 4-32...
Page 127 Enable Response to Selection When this bit is set, the LSI53C876 SCSI function is able to respond to bus-initiated selection at the chip ID in the Response ID Zero (RESPID0)
Page 128 The synchronous transfer period the LSI53C876 should use when transferring SCSI data is determined in the following example. The LSI53C876 is connected to a hard disk which can transfer data at 10 Mbytes/s synchronously. The LSI53C876 SCSI function’s SCLK is running at 40 MHz.
Page 129 Table 4.5 describes the possible combinations and their relationship to the synchronous data offset used by the LSI53C876 SCSI function. These bits determine the LSI53C876 SCSI function’s method of transfer for Data-In and Data-Out phases only; all other information transfers occur asynchronously.
Page 130 Table 4.5 Maximum Synchronous Offset Synchronous Offset 0-Asynchronous Reserved Reserved Reserved Reserved Register: 0x06 SCSI Destination ID (SDID) Read/Write ENC[3:0] Reserved [7:4] Encoded Destination SCSI ID [3:0] Writing these bits sets the SCSI ID of the intended initiator or target during SCSI reselection or selection phases, respectively.
Page 131 12 V power supply to the external ﬂash memory. This bit powers up with the power to the external memory disabled. The LSI Logic PCI to SCSI host adapters use the GPIO4 pin in the process of ﬂashing a new SDMS ROM. SCSI Registers...
Page 132 LSI Logic SDMS software uses the GPIO0 pin to toggle SCSI device LEDs, turning on the LED whenever the LSI53C876 SCSI function is on the SCSI bus. SDMS software drives this pin low to turn on the LED, or drives it high to turn off the LED.
Page 133 SCSI SCRIPTS. SOCL is used only when transferring data using programmed I/O. Some bits are set (1) or reset (0) when executing SCSI SCRIPTS. Do not write to the register once the LSI53C876 SCSI function starts executing normal SCSI SCRIPTS.
Page 134 Encoded Destination SCSI ID [3:0] Reading the SSID register immediately after the LSI53C876 SCSI function is selected or reselected returns the binary-encoded SCSI ID of the device that performed the operation. These bits are invalid for targets that are selected under the single initiator option of the SCSI-1 speciﬁcation.
Page 135 Register: 0x0B SCSI Bus Control Lines (SBCL) Read Only SREQ/ Status SACK/ Status SBSY/ Status SSEL/ Status SATN/ Status SMSG/ Status SC_D/ Status SI_O/ Status This register returns the SCSI control line status. A bit is set when the corresponding SCSI control line is asserted. These bits are not latched; they are a true representation of what is on the SCSI bus at the time the register is read.
Page 136 MDPE Master Data Parity Error This bit is set when the LSI53C876 SCSI function as a master detects a data parity error, or a target device signals a parity error during a data phase. This bit is completely disabled by the Master Parity Error Enable bit...
Page 137 SCSI SCRIPTS. Any of the following conditions during instruction execution also set this bit: • The LSI53C876 SCSI function is executing a Wait Disconnect instruction and the SCSI REQ line is asserted without a disconnect occurring. • A Block Move instruction is executed with 0x000000...
Page 138 • A Load/Store instruction is issued with the memory address mapped to the operating registers of the chip, not including ROM or RAM. • A Load/Store instruction is issued when the register address is not aligned with the memory address. •...
Page 139 Arbitration in Progress Arbitration in Progress (AIP = 1) indicates that the LSI53C876 SCSI function has detected a Bus Free condition, asserted BSY, and asserted its SCSI ID onto the SCSI bus. Lost Arbitration...
Page 140 These four bits, along with SCSI Status Two (SSTAT2), bit 4, deﬁne the number of bytes or words that currently reside in the LSI53C876 SCSI synchronous data FIFO as shown in Table 4.6. These bits are not latched and they will change as data moves through the FIFO.
Page 141 Table 4.6 SCSI Synchronous Data FIFO Word Count (Cont.) Bytes or Words in the SCSI (SSTAT2 bit 4) FIFO SDP0L Latched SCSI Parity This bit reﬂects the SCSI parity signal (SDP0/), corresponding to the data latched in the SCSI Input Data Latch (SIDL) register.
Page 142 Register: 0x0F SCSI Status Two (SSTAT2) Read Only ORF1 OLF1 SPL1 LDSC SDP1 ILF1 SIDL Most Signiﬁcant Byte Full This bit is set when the most signiﬁcant byte in the SCSI Input Data Latch (SIDL) register contains data. Data is transferred from the SCSI bus to the SCSI Input Data Latch register before being sent to the DMA FIFO and then to the host bus.
Page 143 SCSI device selects or reselects the LSI53C876 SCSI function. If the Connected bit is asserted and the LDSC bit is asserted, a disconnect is indicated. This bit is set when the Connected bit in SCNTL1 is off.
Page 144 Chapter 2, “Functional Description.” ABRT Abort Operation Setting this bit aborts the current operation under execution by the LSI53C876 SCSI function. If this bit is set and an interrupt is received, clear this bit before reading the DMA Status (DSTAT) register to prevent further aborted interrupts from being generated.
Page 145 The SCRIPTS processor may set this bit using a SCRIPTS register write instruction. An external processor may also set it while the LSI53C876 SCSI function is executing a SCRIPTS operation. This bit enables the SCSI function to notify an external processor of a predeﬁned condition while SCRIPTS are running.
Page 146 This bit must be written to one in order to clear it after it has been set. SCSI Interrupt Pending This status bit is set when an interrupt condition is detected in the SCSI portion of the LSI53C876 SCSI function. The following conditions cause a SCSI interrupt to occur: •...
Page 147 DMA Interrupt Pending This status bit is set when an interrupt condition is detected in the DMA portion of the LSI53C876 SCSI function. The following conditions cause a DMA interrupt to occur: • A PCI parity error is detected •...
Page 148 Register: 0x19 Chip Test One (CTEST1) Read Only FMT[3:0] FFL[3:0] FMT[3:0] Byte Empty in DMA FIFO [7:4] These bits identify the bottom bytes in the DMA FIFO that are empty. Each bit corresponds to a byte lane in the DMA FIFO. For example, if byte lane three is empty, then FMT3 is set.
Page 149 TEOP SCSI True End of Process This bit indicates the status of the LSI53C876 SCSI function’s internal TEOP signal. The TEOP signal acknowledges the completion of a transfer through the SCSI portion of the LSI53C876 SCSI function. When this bit is set, TEOP is active.
Page 150 DACK Data Acknowledge Status This bit indicates the status of the LSI53C876 SCSI function’s internal Data Acknowledge signal (DACK/). When this bit is set, DACK/ is inactive. When this bit is clear, DACK/ is active. Register: 0x1B Chip Test Three (CTEST3)
Page 151 Pointer (DSP) register when a Return instruction is executed. This address points to the next instruction to execute. Do not write to this register while the LSI53C876 SCSI function is executing SCRIPTS. During any Memory-to-Memory Move operation, the contents of this register are preserved. The power-up value of this register is indeterminate.
Page 152 Register: 0x20 DMA FIFO (DFIFO) Read/Write Byte Offset Counter [7:0] These bits, along with bits [1:0] in the Chip Test Five (CTEST5) register, indicate the amount of data transferred between the SCSI core and the DMA core. It determines the number of bytes in the DMA FIFO when an interrupt occurs.
Page 153 MPEE FBL[2:0] BDIS Burst Disable When set, this bit causes the LSI53C876 SCSI function to perform back-to-back cycles for all transfers. When this bit is cleared, back-to-back transfers for opcode fetches and burst transfers for data moves are performed. ZMOD...
Page 154 LSI53C876 SCSI function. A parity error during a bus master write is detected by the target, and the LSI53C876 SCSI function is informed of the error by the PERR/ pin being asserted by the target. When this bit is cleared, the LSI53C876 SCSI function does not interrupt if a master parity error occurs.
Page 155 Register: 0x22 Chip Test Five (CTEST5) Read/Write ADCK BBCK MASR DDIR BO[9:8] ADCK Clock Address Incrementor Setting this bit increments the address pointer contained in the DMA Next Address (DNAD) register. The DNAD register is incremented based on the DNAD contents and the current DBC value.
Page 156 Burst Length, Bit 2 This bit works with bits 6 and 7 in the DMA Mode (DMODE) register to determine the burst length. For complete deﬁnitions of this ﬁeld, refer to the descriptions of DMODE bits 6 and 7. This bit is disabled if an 88-byte FIFO is selected by clearing the DMA FIFO size bit.
Page 157 Block Move and a value of 0x000000 is loaded into the DMA Byte Counter (DBC) register, an illegal instruction interrupt occurs if the LSI53C876 SCSI function is not in target mode, Command phase. DMA Byte Counter (DBC) register also holds the least signiﬁcant 24 bits of the ﬁrst Dword of a SCRIPTS...
Page 158 DCMD DCMD DMA Command [7:0] This 8-bit register determines the instruction for the LSI53C876 SCSI function to execute. This register has a different format for each instruction. For a complete description see Chapter 5, “SCSI SCRIPTS Instruction Set.” Registers: 0x28–0x2B...
Page 159 normal SCRIPTS operation, once the starting address of the SCRIPT is written to this register, SCRIPTS are automatically fetched and executed until an interrupt condition occurs. In single step mode, there is a single step interrupt after each instruction is executed. The DMA SCRIPTS Pointer (DSP) register does not need to be written with the next...
Page 160 The LSI53C876 SCSI function asserts the Bus Request (REQ/) output when the DMA FIFO can accommodate a transfer of at least one burst size of data.
Page 161 I/O space; and if cleared, then the source address is in memory space. This function is useful for register-to-memory operations using the Memory Move instruction when a LSI53C876 SCSI function is I/O mapped. Bits 4 and 5 of the Chip Test Two (CTEST2) register determine the conﬁguration...
Page 162 Multiple command is used on all read cycles when it is legal. Burst Opcode Fetch Enable Setting this bit causes the LSI53C876 SCSI function to fetch instructions in burst mode. Speciﬁcally, the chip bursts in the ﬁrst two Dwords of all instructions using a single bus ownership.
Page 163 Register: 0x39 DMA Interrupt Enable (DIEN) Read/Write MDPE ABRT Reserved MDPE Master Data Parity Error Bus Fault ABRT Aborted Single Step Interrupt SCRIPTS Interrupt Instruction Received Reserved Illegal Instruction Detected This register contains the interrupt mask bits corresponding to the interrupting conditions described in the DMA Status (DSTAT) register.
Page 164 CLSE PFEN INTM INTD CLSE Cache Line Size Enable Setting this bit enables the LSI53C876 SCSI function to sense and react to cache line boundaries set up by the DMA Mode (DMODE) or PCI Cache Line Size register, whichever contains the smaller value. Clearing this bit...
Page 165 SCRIPTS Pointer (DSP) register when this bit is set. This bit is required if the LSI53C876 SCSI function is in one of the following modes: • Manual start mode – Bit 0 in the...
Page 166 Chapter 2, “Functional Description.” LSI53C700 Family Compatibility When the COM bit is cleared, the LSI53C876 SCSI function behaves in a manner compatible with the LSI53C700 family; selection/reselection IDs are stored in both the SCSI Selector ID (SSID)
Page 167 SCSI Phase Mismatch - Initiator Mode; SCSI ATN Condition - Target Mode Setting this bit allows the LSI53C876 to generate an interrupt when a Phase Mismatch or ATN condition occurs. In initiator mode, this bit is set when the SCSI...
Page 168 Reselected Setting this bit allows the LSI53C876 to generate an interrupt when the LSI53C876 has been reselected by another SCSI device. Set the Enable Response to Reselection bit in the SCSI Chip ID (SCID) register for this to occur. SCSI Gross Error Setting this bit allows the LSI53C876 to generate an interrupt when a SCSI gross error occurs.
Page 169 SCSI Reset Condition Setting this bit allows the LSI53C876 to generate an interrupt when the SRST/ signal has been asserted by the LSI53C876 or any other SCSI device. This condition is edge-triggered, so multiple interrupts cannot occur because of a single SRST/ pulse.
Page 170 General Purpose Timer Expired Setting this bit allows the LSI53C876 to generate an interrupt when the general purpose timer has expired. The time measured is the time between enabling and disabling of the timer. See the description of the SCSI...
Page 171 This bit is set when an arbitration only or full arbitration sequence is completed. Selected This bit is set when the LSI53C876 SCSI function is selected by another SCSI device. The Enable Response to Selection bit must be set in the SCSI Chip ID (SCID) register (and the RESPID register must hold the chip’s...
Page 172 FIFO. Unexpected Disconnect This bit is set when the LSI53C876 SCSI function is operating in initiator mode and the target device unexpectedly disconnects from the SCSI bus. This bit is only valid when the LSI53C876 SCSI function operates in the initiator mode.
Page 173 Reading the SIST1 clears the interrupt condition. Reserved [7:3] Selection or Reselection Time-out The SCSI device which the LSI53C876 SCSI function is attempting to select or reselect does not respond within the programmed time-out period. See the description of SCSI Timer Zero (STIME0) register, bits [3:0], for more information on the time-out timer.
Page 174 Register: 0x44 SCSI Longitudinal Parity (SLPAR) Read/Write SLPAR SLPAR SCSI Longitudinal Parity [7:0] This register performs a bytewise longitudinal parity check on all SCSI data received or sent through the SCSI core. If one of the bytes received or sent (usually the last) is the set of correct even parity bits, SLPAR should go to zero (assuming it started at zero).
Page 175 The longitudinal parity checks are meant to provide an added measure of SCSI data integrity and are entirely optional. This register does not latch SCSI selection/reselection IDs under any circumstances. The default value of this register is zero. The longitudinal parity function normally operates as a byte function.
Page 176 Register: 0x46 Memory Access Control (MACNTL) Read/Write TYP[3:0] TYP[3:0] Chip Type [7:4] These bits identify the chip type for software purposes. This technical manual applies to devices that have these bits set to 0x70. Reserved [3:0] Register: 0x47 General Purpose Pin Control (GPCNTL) Read/Write GPIO[4:2] GPIO[1:0]...
Page 177 Reserved GPIO[4:2] GPIO Enable [4:2] General purpose control, corresponding to bit 4 in the General Purpose (GPREG) register and the GPIO4 pin. GPIO4 powers-up as a general purpose output, and GPIO[3:2] power-up as general purpose inputs. GPIO[1:0] GPIO Enable [1:0] These bits power-up set, causing the GPIO1 and GPIO0 pins to become inputs.
Page 178 Minimum Time-out Minimum Time-out HTH[7:4] (80 MHz Clock) With (80 MHz Clock) SEL[3:0] Scale Factor Bit With Scale Factor GEN[3:0] Cleared Bit Set 0000 Disabled Disabled 100 µs 0001 1.6 ms 200 µs 0010 3.2 ms 400 µs 0011 6.4 ms 800 µs 0100 12.8 ms...
Page 179 Register: 0x49 SCSI Timer One (STIME1) Read/Write HTHBA GENSF HTHSF GEN[3:0] Reserved HTHBA Handshake-to-Handshake Timer Bus Activity Enable Setting this bit causes this timer to begin testing for SCSI REQ/, ACK/ activity as soon as SBSY/ is asserted, regardless of the agents participating in the transfer. GENSF General Purpose Timer Scale Factor Setting this bit causes this timer to shift by a factor of 16.
Page 180 Register: 0x4A Response ID Zero (RESPID0) Read/Write RESPID0 Response ID Zero [7:0] RESPID0 and RESPID1 contain the selection or reselection IDs. In other words, these two 8-bit registers contain the ID that the chip responds to on the SCSI bus. Each bit represents one possible ID with the most signiﬁcant bit of RESPID1 representing ID 15 and the least signiﬁcant bit of RESPID0 representing ID 0.
Page 181 SCSI selection or reselection phase. These bits are read only and contain the encoded value of 0–15 possible IDs that could be used to select the LSI53C876 SCSI function. During a SCSI selection or reselection phase when a valid ID is put on the bus, and the LSI53C876 SCSI function responds to that ID, the “selected as”...
Page 182 It is used in low level synchronous SCSI operations. When this bit is set, the LSI53C876 SCSI function, as a target, is waiting for the initiator to acknowledge the data transfers. If the LSI53C876 SCSI function is an initiator, then the target has sent the offset number of requests.
Page 183 SCLK for use as the internal SCSI clock. Reserved [1:0] The LSI53C876 SCSI clock doubler doubles a 40 MHz SCSI clock, increasing the frequency to 80 MHz. Follow these steps to use the clock doubler. 1. Set the SCLK Doubler Enable bit (SCSI Test One (STEST1), bit 3).
Page 184 SCSI Output Control Latch (SOCL) SCSI Output Data Latch (SODL) registers regardless of whether the LSI53C876 SCSI function is conﬁgured as a target or initiator. Note: Do not set this bit during normal operation, since it could cause contention on the SCSI bus.
Page 185 5 megatransfers per second) operations, because a valid assertion could be treated as a glitch. SCSI Low level Mode Setting this bit places the LSI53C876 SCSI function in low level mode. In this mode, no DMA operations occur, and no SCRIPTS execute. Arbitration and selection may...
Page 186 LSI53C876 SCSI function is driving these signals. Active deassertion of these signals occurs only when the LSI53C876 SCSI function is in an information transfer phase. When operating in a differential environment or at fast SCSI timings, TolerANT Active negation should be enabled to improve setup and deassertion times.
Page 187 Disable Single Initiator Response If this bit is set, the LSI53C876 SCSI function ignores all bus-initiated selection attempts that employ the single initiator option from SCSI-1. In order to select the LSI53C876 SCSI function while this bit is set, the LSI53C876 SCSI function’s SCSI ID and the initiator’s...
Page 188 SCSI Output Data Latch (SODL) register and then read back into the LSI53C876 by reading this register to allow loopback testing. When receiving SCSI data, the data ﬂows into this register and out to the host FIFO. This register differs...
Page 189 Registers: 0x54–0x55 SCSI Output Data Latch (SODL) Read/Write SODL SODL SCSI Output Data Latch [15:0] This register is used primarily for diagnostic testing or programmed I/O operation. Data written to this register is asserted onto the SCSI data bus by setting the Assert Data Bus bit in the SCSI Control One (SCNTL1) register.
Page 190 Registers: 0x5C–0x5F Scratch Register B (SCRATCHB) Read/Write SCRATCHB SCRATCHB Scratch Register B [31:0] This is a general purpose user deﬁnable scratch pad register. Apart from CPU access, only register Read/Write and Memory Moves directed at the SCRATCH register alter its contents. When bit 3 in the Chip Test Two (CTEST2) register is set, this register contains the base address for the 4 Kbytes internal RAM.
Page 191: Chapter 5 Scsi Scripts Instruction Set
Chapter 5 SCSI SCRIPTS Instruction Set After power up and initialization, the LSI53C876 can be operated in the low level register interface mode or in the high level SCSI SCRIPTS mode. Chapter 5 is divided into the following sections: •...
Page 192: High Level Scsi Scripts Mode
5.2 High Level SCSI SCRIPTS Mode To operate in the SCSI SCRIPTS mode, the LSI53C876 requires only a SCRIPTS start address. The start address must be at a Dword (four byte) boundary. This aligns subsequent SCRIPTS at a Dword boundary since all SCRIPTS are 8 or 12 bytes long.
Page 193: Sample Operation
• Loading the DMA SCRIPTS Pointer (DSP) register causes the LSI53C876 to fetch its ﬁrst instruction at the address just loaded. This fetch is from main memory or the internal RAM, depending on the address. High Level SCSI SCRIPTS Mode...
Page 194 LSI53C876 requests use of the PCI bus again to transfer the data. • When the LSI53C876 is granted the PCI bus, it executes (as a bus master) a burst transfer (programmable size) of data, decrements the internally stored remaining byte count, increments the address pointer, and then releases the PCI bus.
Page 195 ATN0, alt_addr Fetch move 1, identify_msg_buf, when MSG_OUT SCRIPTS SCSI move 6, cmd_buf, when CMD LSI53C876 move 512, data_buf, when DATA_OUT move 1, stat_in_buf, when STATUS move 1, msg_in_buf, when MSG_IN move SCNTL2 & 7F to SCNTL2 clear ACK...
Page 196 5.3 Block Move Instruction Performing a Block Move instruction, bit 5, Source I/O - Memory Enable (SIOM) and bit 4, Destination I/O - Memory Enable (DIOM) in the Mode (DMODE) register determines whether the source/destination address resides in memory or I/O space. When data is moved onto the SCSI bus, SIOM controls whether that data comes from I/O or memory space.
Page 197 Once the data pointer address is loaded, it is executed as when the chip operates in the direct mode. This indirect feature allows speciﬁcation of a table of data buffer addresses. Using the SCSI SCRIPTS compiler, the table offset is placed in the script at compile time. Then at the actual data transfer time, the offsets are added to the base address of the data address table by the external processor.
Page 198: Block Move Instruction Register
For a MOVE instruction, the 24-bit byte count is fetched from system memory. Then the 32-bit physical address is brought into the LSI53C876. Execution of the move begins at this point. SCSI SCRIPTS Instruction Set...
Page 199 MOVE CHMOV These instructions perform the following steps: 1. The LSI53C876 veriﬁes that it is connected to the SCSI bus as a Target before executing this instruction. 2. The LSI53C876 asserts the SCSI phase signals (SMSG/, SC_D/, and SI_O/) as deﬁned by the Phase Field bits in the instruction.
Page 200 Command Descriptor Block: 6, 10, or 12 bytes. If the VUE0 bit is set, the LSI53C876 receives the number of bytes in the byte count regardless of the group code. – If any other Group Code is received, the...
Page 201 Instruction Deﬁned CHMOV MOVE These instructions perform the following steps: 1. The LSI53C876 veriﬁes that it is connected to the SCSI bus as an Initiator before executing this instruction. 2. The LSI53C876 waits for an unserviced phase to occur. An unserviced phase is any phase (with SREQ/ asserted) for which the LSI53C876 has not yet transferred data by responding with a SACK/.
Page 202 Set ATN instruction), the LSI53C876 deasserts SATN/ during the ﬁnal SREQ/SACK/ handshake. 7. When the LSI53C876 is performing a block move for Message-In phase, it does not deassert the SACK/ signal for the last SREQ/SACK/ handshake. Clear the SACK/ signal using the Clear SACK I/O instruction.
Page 203 [31:30] OPC[2:0] OpCode [29:27] The following OpCode bits have different meanings, depending on whether the LSI53C876 is operating in initiator or target mode. OpCode selections 101–111 are considered Read/Write instructions, and are described in Section 5.5, “Read/Write Instructions.” I/O Instruction...
Page 204 32-bit jump address ﬁeld stored in the DMA Next Address (DNAD) register. Manually set the LSI53C876 to Initiator mode if it is reselected, or to Tar- get mode if it is selected. Disconnect Instruction The LSI53C876 disconnects from the SCSI bus by deasserting all SCSI signal outputs.
Page 205 32-bit jump address ﬁeld stored in the DMA Next Address (DNAD) register. Manually set the LSI53C876 to Initiator mode when it is reselected. If the CPU sets the SIGP bit in the SCSI Status Zero...
Page 206: I/O Instruction Register
Figure 5.3 I/O Instruction Register DCMD Register DBC Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Set/Clear ATN/ Set/Clear ACK/ Set/Clear Target Mode...
Page 207 32-bit jump address ﬁeld stored in the DMA Next Address (DNAD) register. Manually set the LSI53C876 to Initiator mode if it is reselected, or to Tar- get mode if it is selected. If the Select with SATN/ ﬁeld is set, the SATN/ signal is asserted during the selection phase.
Page 208 Wait Reselect Instruction If the LSI53C876 is selected before being reselected, it fetches the next instruction from the address pointed to by the 32-bit jump address ﬁeld stored in the DMA Next Address (DNAD) register. Manually set the LSI53C876 to Target mode when it is selected.
Page 209 Data Structure Address (DSA) register, and used as an offset relative to the value in the DSA register. The SCSI Control Three (SCNTL3) value, SCSI ID, synchronous offset and synchronous period are loaded from this address. Prior to the start of an I/O, load the Data Struc- ture Address (DSA) with the base address of the I/O data...
Page 210 Select with ATN/ This bit speciﬁes whether SATN/ is asserted during the selection phase when the LSI53C876 is executing a Select instruction. When operating in Initiator mode, set this bit for the Select instruction. If this bit is set on any other I/O instruction, an illegal instruction interrupt is generated.
Page 211 This bit is used in conjunction with a Set or Clear instruction to set or clear Target mode. Setting this bit with a Set instruction conﬁgures the LSI53C876 as a Target device (this sets bit 0 of the SCSI Control Zero (SCNTL0) register).
Page 212 The Set/Clear SCSI ACK/ATN instruction is used after message phase Block Move operations to give the Initiator the opportunity to assert attention before acknowledging the last message byte. For example, if the Initiator wishes to reject a message, it issues an Assert SCSI ATN instruction before a Clear SCSI ACK instruction.
Page 213: Read/Write Instruction Register
Figure 5.4 Read/Write Instruction Register DCMD Register DBC Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Immediate Data Reserved (must be 0) Register...
Page 214 [22:16] It is possible to change register values from SCRIPTS in read-modify-write cycles or move to/from SFBR cycles. A[6:0] selects an 8-bit source/destination register within the LSI53C876. ImmD Immediate Data [15:8] This 8-bit value is used as a second operand in logical and arithmetic functions.
Page 215 Subtraction is not available when SCSI First Byte Received (SFBR) used instead of data8 in the instruction syntax. To subtract one value from another when using SFBR, ﬁrst XOR the value to subtract (subtrahend) with 0xFF, and add 1 to the resulting value. This creates the 2’s complement of the subtrahend.
Page 216 Table 5.2 Read/Write Instructions (Cont.) Opcode 111 Opcode 110 Opcode 101 Operator Read-Modify-Write Move to SFBR Move from SFBR OR data with register and OR data with register and OR data with SFBR and place the result in the same place the result in the SCSI place the result in the...
Page 217 Return Interrupt Reserved Jump Instruction The LSI53C876 can do a true/false comparison of the ALU carry bit, or compare the phase and/or data as deﬁned by the Phase Compare, Data Compare and True/False bit ﬁelds. If the comparisons are true, then it loads the...
Page 218 Call Instruction The LSI53C876 can do a true/false comparison of the ALU carry bit, or compare the phase and/or data as deﬁned by the Phase Compare, Data Compare, and True/False bit ﬁelds. If the comparisons are true, it loads the...
Page 219: Transfer Control Instruction
Figure 5.5 Transfer Control Instruction DCMD Register DBC Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mask for Compare Data to be compared with the SCSI First...
Page 220 Return Instruction The LSI53C876 can do a true/false comparison of the ALU carry bit, or compare the phase and/or data as deﬁned by the Phase Compare, Data Compare, and True/False bit ﬁelds. If the comparisons are true, it loads the...
Page 221 SCSI phase actually being driven on the SCSI bus. The following table describes the possible combinations and their corresponding SCSI phase. These bits are only valid when the LSI53C876 is operating in Initiator mode. Clear these bits when the LSI53C876 is operating in the Target mode.
Page 222 The SCRIPTS program counter is a 32-bit value pointing to the SCRIPTS currently under execution by the LSI53C876. The next address is formed by adding the 32-bit program counter to the 24-bit signed value of the last 24 bits of the Jump or Call instruction. Because it is signed (2’s complement), the jump can be forward or...
Page 223 LSI53C876 is operating in Target mode this bit is set when it tests for an active SCSI SATN/ signal. Wait For Valid Phase If the Wait for Valid Phase bit is set, the LSI53C876 waits for a previously unserviced phase before comparing the SCSI phase and data.
Page 224 The Memory Move instruction is used to copy the speciﬁed number of bytes from the source address to the destination address. Allowing the LSI53C876 to perform memory moves frees the system processor for other tasks and moves data at higher speeds than available from current DMA controllers.
Page 225 These bits are reserved and must be zero. If any of these bits are set, an illegal instruction interrupt occurs. No Flush When this bit is set, the LSI53C876 performs a Memory Move without ﬂushing the prefetch unit. When this bit is cleared, the Memory Move instruction automatically ﬂushes the prefetch unit.
Page 226 Memory Move. However, it can be loaded using SCRIPTS Read/Write operations. To load the SFBR with a byte stored in system memory, ﬁrst move the byte to an intermediate LSI53C876 register (for example, a SCRATCH register), and then to the...
Page 227: Memory Move Instruction
Figure 5.6 Memory Move Instruction DCMD Register DBC Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 No Flush 24-Bit Memory Move Byte Counter 0 (Reserved)
Page 228 5.8 Load and Store Instructions The Load and Store instruction provides a more efﬁcient way to move data from/to memory to/from an internal register in the chip without using the normal memory move instruction. The Load and Store instructions are represented by two Dword opcodes. The ﬁrst Dword contains the DMA Command (DCMD) DMA Byte...
Page 229 Reserved [27:26] No Flush (Store instruction only) When this bit is set, the LSI53C876 performs a Store without ﬂushing the prefetch unit. When this bit is cleared, the Store instruction automatically ﬂushes the prefetch unit. Use No Flush if the source and destination are not within four instructions of the current Store instruction.
Page 230 5.8.2 Second Dword Memory I/O Address / DSA Offset [31:0] This is the actual memory location of where to Load and Store, or the offset from the Data Structure Address (DSA) register value. Figure 5.7 illustrates the Load and Store Instruction format.
Page 231: Load And Store Instruction Format
Figure 5.7 Load and Store Instruction Format DCMD Register DBC Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Byte Count (must be 0)
Page 232 5-42 SCSI SCRIPTS Instruction Set...
Page 233 • Section 6.4, “AC Characteristics” • Section 6.5, “Package Diagrams” 6.1 DC Characteristics This section of the manual describes the LSI53C876 DC characteristics. Table 6.1 through Table 6.15 give current and voltage speciﬁcations. These characteristics apply whenever a VDD source of 5 V is supplied to the pins below.
Page 234 Table 6.1 Absolute Maximum Stress Ratings Symbol Parameter Unit Test Conditions −55 °C Storage temperature – −0.5 Supply voltage – −0.5 Input voltage +0.5 – ±150 Latch-up current – – Electrostatic discharge – MIL-STD 883C, Method 3015.7 1. − 2 V < V <...
Page 235 Table 6.3 SCSI Signals—SD[15:0]/, SDP[1:0]/, SREQ/, SACK/ Symbol Parameter Unit Test Conditions Input high voltage +0.5 – −0.5 Input low voltage – Output high voltage 2.5 mA Output low voltage 48 mA −10 µA 3-state leakage – 1. TolerANT active negation enabled. Table 6.4 SCSI Signals—SMSG, SI_O/, SC_D/, SATN/, SBSY/, SSEL/, SRST/ Symbol...
Page 236 Table 6.6 Capacitance Symbol Parameter Unit Test Conditions Input capacitance of input pads – – Input capacitance of I/O pads – – Table 6.7 Output Signals—INTA/, INTB/ Symbol Parameter Unit Test Conditions −16 mA Output high voltage Output low voltage 16 mA −200 −50...
Page 237 Table 6.9 Output Signal—REQ/ Symbol Parameter Unit Test Conditions −16 mA Output high voltage Output low voltage 16 mA −10 µA 3-state leakage – Note: REQ/ has a 25 µA pull-up that is enabled when TESTIN is low. Table 6.10 Output Signal—SERR/ Symbol Parameter Unit...
Page 238 Table 6.12 Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/, GPIO2, GPIO3, GPIO4 Symbol Parameter Unit Test Conditions Input high voltage +0.5 – −0.5 Input low voltage – −16 mA Output high voltage Output low voltage 16 mA −200 µA 3-state leakage – Table 6.13 Bidirectional Signals—MAD[7:0] Symbol Parameter...
Page 239 Table 6.19 give current and voltage speciﬁcations. These characteristics apply whenever a VDD source of 3.3 V is supplied to the VDD-I pins of the LSI53C876. Table 6.16 Bidirectional Signals—AD[31:0], C_BE[3:0]/, FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR Symbol Parameter...
Page 240 3-state leakage – 6.3 TolerANT Technology Electrical Characteristics The LSI53C876 features TolerANT technology, which includes active negation on the SCSI drivers and input signal ﬁltering on the SCSI receivers. Active negation actively drives the SCSI Request, Acknowledge, Data, and Parity signals HIGH rather than allowing them to be passively pulled up by terminators.
Page 241 Table 6.20 TolerANT Technology Electrical Characteristics Symbol Parameter Unit Test Conditions Output high voltage = 2.5 mA Output low voltage = 48 mA Input high voltage – −0.5 Input low voltage Referenced to V −0.66 −0.77 = −20 mA Input clamp voltage = 4.75;...
Page 242 Figure 6.1 Rise and Fall Time Test Conditions 47 Ω 20 pF 2.5 V − Figure 6.2 SCSI Input Filtering REQ/ or ACK/ Input Note: t is the input ﬁltering period. Figure 6.3 Hysteresis of SCSI Receivers Input Voltage (Volts) 6-10 Electrical Characteristics...
Page 243 Figure 6.4 Input Current as a Function of Input Voltage 14.4 V 8.2 V − 0.7 V HIGH-Z OUTPUT −20 ACTIVE −40 −4 Input Voltage (Volts) Figure 6.5 Output Current as a Function of Output Voltage −200 −400 −600 −800 Output Voltage (Volts) Output Voltage (Volts) TolerANT Technology Electrical Characteristics...
Page 244: Clock Timing
6.4 AC Characteristics The AC characteristics described in this section apply over the entire range of operating conditions (refer to Section 6.1, “DC Characteristics”). Chip timing is based on simulation at worst case voltage, temperature, and processing. This part of the chapter contains AC Characteristics for the PCI Interface and the SCSI Interface.
Page 245: Reset Input
Table 6.22 Figure 6.7 provide Reset Input timing data. Table 6.22 Reset Input Symbol Parameter Unit Reset pulse width – Reset deasserted setup to CLK HIGH – MAD setup time to CLK HIGH – (for conﬁguring the MAD bus only) MAD hold time from CLK HIGH –...
Page 246: Interrupt Output
Table 6.23 Figure 6.8 provide Interrupt Output timing data. Table 6.23 Interrupt Output Symbol Parameter Unit CLK HIGH to IRQ/ LOW – CLK HIGH to IRQ/ HIGH – INTA/, INTB/ deassertion time – CLKs Figure 6.8 Interrupt Output INTA/, INTB/ 6-14 Electrical Characteristics...
Page 247: Target Read, From External Memory
Figure 6.29 represent signal activity when the LSI53C876 accesses the PCI bus. This section includes timing diagrams for access to three groups of external memory conﬁgurations. The ﬁrst group applies to systems with memory size of 128 Kbytes and above;...
Page 248: Read Cycle, Normal/Fast Memory (≥ 128 Kbyte), Multiple Byte Access
6.4.1.1 3.3 V PCI Timings Note: When a 3.3 V source is applied to the V -I pins of the LSI53C876, some of the PCI timing data in Table 6.24 through Table 6.35 will change. The 3.3 V PCI timing data...
Page 249: Conﬁguration Register Read
(Driven by Master-Addr; Data Out LSI53C876-Data) Add In C_BE/ Byte Enable (Driven by Master) (Driven by Master-Addr; LSI53C876-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C876) STOP/ (Driven by LSI53C876) DEVSEL/ (Driven by LSI53C876) IDSEL (Driven by Master) AC Characteristics 6-17...
Page 250: Conﬁguration Register Write
(Driven by Master) Data Out Add In C_BE/ Byte Enable (Driven by Master) PAR/ (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C876) STOP/ (Driven by LSI53C876) DEVSEL/ (Driven by LSI53C876) IDSEL (Driven by Master) 6-18 Electrical Characteristics...
Page 251: Target Read (Not From External Memory)
(Driven by Master) Data (Driven by Master-Addr; LSI53C876-Data) Add In C_BE/ Byte Enable (Driven by Master) PAR/ (Driven by Master-Addr; LSI53C876 Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C876) STOP/ (Driven by LSI53C876) DEVSEL/ (Driven by LSI53C876) AC Characteristics 6-19...
Page 252 FRAME/ (Driven by Master) (Driven by Master) Data Out Add In C_BE/ Byte Enable (Driven by Master) PAR/ (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C876) STOP/ (Driven by LSI53C876) DEVSEL/ (Driven by LSI53C876) 6-20 Electrical Characteristics...
Page 253 Table 6.29 Target Read (From External Memory) Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid – Side signal input setup time – Address setup to MAS/ high –...
Page 254 (Driven by Master) TRDY/ (Driven by LSI53C876) STOP/ (Driven by LSI53C876) DEVSEL/ (Driven by LSI53C876) Middle Order Low Order (Addr driven by LSI53C876 High Order Address Address Address Data driven by Memory) MAS1/ (Driven by LSI53C876) MAS0/ (Driven by LSI53C876)
Page 255 IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C876) STOP/ (Driven by LSI53C876) DEVSEL/ (Driven by LSI53C876) Data In (Addr driven by LSI53C876 Data driven by Memory) MAS1/ (Driven by LSI53C876) MAS0/ (Driven by LSI53C876) MCE/ (Driven by LSI53C876) MOE/ (Driven by LSI53C876)
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Page 257 Table 6.30 Target Write (From External Memory) Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid – Address setup to MAS/ high – Address hold from MAS/ high –...
Page 258 Add In C_BE/ Byte Enable (Driven by Master) PAR/ (Driven by Master-Addr; LSI53C876-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C876) STOP/ (Driven by LSI53C876) DEVSEL/ (Driven by LSI53C876) MAD/ Middle Order Low Order High Order Address (Driven by LSI53C876)
Page 259 C_BE/ Byte Enable Byte Enable (Driven by Master) PAR/ (Driven by Master-Addr; LSI53C876-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C876) STOP/ (Driven by LSI53C876) DEVSEL/ (Driven by LSI53C876) MAD/ Data Out (Driven by LSI53C876) MAS1/ (Driven by LSI53C876) MAS0/...
Page 260: Opcode Fetch, Nonburst
Table 6.31 Opcode Fetch, Nonburst Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid – Side signal input setup time – Side signal input hold time – CLK to side signal output valid –...
Page 261 Figure 6.15 Opcode Fetch, Nonburst (Driven by System) GPIO0_FETCH/ (Driven by LSI53C876) GPIO1_MASTER/ (Driven by LSI53C876) REQ/ (Driven by LSI53C876) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C876) Addr Data Addr Data (Driven by LSI53C876 C_BE/ CMD BE CMD BE...
Page 262: Opcode Fetch, Burst
Table 6.32 Opcode Fetch, Burst Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid – Side signal input setup time – Side signal input hold time – CLK to side signal output valid –...
Page 263 Figure 6.16 Opcode Fetch, Burst (Driven by System) GPIO0_FETCH/ (Driven by LSI53C876) GPIO1_MASTER/ (Driven by LSI53C876) REQ/ (Driven by LSI53C876) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C876) (Driven by LSI53C876- Addr Out Addr; Target-Data) Data In Data In C_BE/...
Page 264: Back-To-Back Read
Table 6.33 Back-to-Back Read Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid – Side signal input setup time – Side signal input hold time – CLK to side signal output valid –...
Page 265 Figure 6.17 Back-to-Back Read (Driven by System) GPIO0_FETCH/ (Driven by LSI53C876) GPIO1_MASTER/ (Driven by LSI53C876) REQ/ (Driven by LSI53C876) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C876) Addr Addr (Driven by LSI53C876- Addr; Target-Data) Data In Data In C_BE/ (Driven by LSI53C876)
Page 266: Back-To-Back Write
Table 6.34 Back-to-Back Write Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid – Side signal input setup time – Side signal input hold time – CLK to side signal output valid –...
Page 267 Figure 6.18 Back-to-Back Write (Driven by System) GPIO0_FETCH/ (Driven by LSI53C876) GPIO1_MASTER/ (Driven by LSI53C876) REQ/ (Driven by LSI53C876) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C876) Addr Data Addr Data (Driven by LSI53C876) C_BE/ (Driven by LSI53C876) PAR/ (Driven by LSI53C876)
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Page 269: Burst Read
Table 6.35 Burst Read Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid – Side signal input setup time – Side signal input hold time – CLK to side signal output valid –...
Page 270 Figure 6.19 Burst Read GPIO0_FETCH/ (Driven by LSI53C876) GPIO1_MASTER/ (Driven by LSI53C876) REQ/ (Driven by LSI53C876) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C876) Addr Addr (Driven by LSI53C876- Addr; Target-Data) Data In C_BE/ (Driven by LSI53C876) PAR/ (Driven by LSI53C876- Addr;...
Page 271 Figure 6.19 Burst Read (Cont.) GPIO0_FETCH/ (Driven by LSI53C876) GPIO1_MASTER/ (Driven by LSI53C876) REQ/ (Driven by LSI53C876) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C876) Data In Data In Addr (Driven by LSI53C876- Addr; Target-Data) C_BE/ (Driven by LSI53C876) PAR/ (Driven by LSI53C876- Addr;...
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Page 273: Burst Write
Table 6.36 Burst Write Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid – Side signal input setup time – Side signal input hold time – CLK to side signal output valid –...
Page 274 Figure 6.20 Burst Write (Driven by System) GPIO0_FETCH/ (Driven by LSI53C876) GPIO1_MASTER/ (Driven by LSI53C876) REQ/ (Driven by LSI53C876) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C876) Addr Data Addr Data (Driven by LSI53C876) C_BE/ (Driven by LSI53C876) PAR/ (Driven by LSI53C876)
Page 275 Figure 6.20 Burst Write (Cont.) (Driven by System) GPIO0_FETCH/ (Driven by LSI53C876) GPIO1_MASTER/ (Driven by LSI53C876) REQ/ (Driven by LSI53C876) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C876) Data Addr Data (Driven by LSI53C876) C_BE/ (Driven by LSI53C876) PAR/ (Driven by LSI53C876)
Page 276 Data setup to CLK high – Figure 6.21 Read Cycle, Normal/Fast Memory (≥ 128 Kbytes), Single Byte Access MAD/ (Addr driven by Middle High Order Low Order Order LSI53C876- Data driven Address Address Address by Memory) Valid Read Data MAS1/ (Driven by LSI53C876) MAS0/...
Page 277: Write Cycle, Normal/Fast Memory (≥ 128 Kbytes), Single Byte Access
MWE/ high to MCE/ high – Figure 6.22 Write Cycle, Normal/Fast Memory (≥ 128 Kbytes), Single Byte Access MAD/ Middle High Order Low Order Valid Write Data Order (Driven by LSI53C876) Address Address Address MAS1/ (Driven by LSI53C876) MAS0/ (Driven by LSI53C876) MCE/...
Page 278 TRDY/ (Driven by LSI53C876) STOP/ (Driven by LSI53C876) DEVSEL/ (Driven by LSI53C876) MAD/ High Order Middle Order Low Order (Addr driven by LSI53C876; Address Address Address Data driven by Memory) MAS1/ (Driven by LSI53C876) MAS0/ (Driven by LSI53C876) MCE/ (Driven by LSI53C876)
Page 279 TRDY/ (Driven by LSI53C876) STOP/ (Driven by LSI53C876) DEVSEL/ (Driven by LSI53C876) MAD/ Low Order Data Data (Addr driven by LSI53C876; Address Data driven by Memory) MAS1/ (Driven by LSI53C876) MAS0/ (Driven by LSI53C876) MCE/ (Driven by LSI53C876) MOE/ (Driven by LSI53C876)
Page 280 LSI53C876-Data) C_BE/ Byte Enable (Driven by Master) PAR/ (Driven by Master-Addr; LSI53C876-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C876) STOP/ (Driven by LSI53C876) DEVSEL/ (Driven by LSI53C876) MAD/ High Order Middle Order Low Order Data Out (Driven by LSI53C876)
Page 281 Data In LSI53C876-Data) C_BE/ Byte Enable (Driven by Master) PAR/ (Driven by Master-Addr; LSI53C876-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C876) STOP/ (Driven by LSI53C876) DEVSEL/ (Driven by LSI53C876) MAD/ Low Order (Driven by LSI53C876) Data Out Address MAS1/...
Page 282: Read Cycle, Slow Memory (≥ 128 Kbytes)
Data setup to CLK high – Figure 6.25 Read Cycle, Slow Memory (≥ 128 Kbytes) MAD/ (Addr driven by Middle High Order Order Order LSI53C876- Data driven Address Address Address by Memory) Valid Read Data MAS1/ (Driven by LSI53C876) MAS0/...
Page 283 – MWE/ high to MCE/ high – Figure 6.26 Write Cycle, Slow Memory (≥ 128 Kbytes) Middle High Order Valid Write Data Order Order (Driven by LSI53C876) Address Address Address MAS1/ (Driven by LSI53C876) MAS0/ (Driven by LSI53C876) MCE/ (Driven by LSI53C876)
Page 284 Address out from MOE/, MCE/ high – Data setup to CLK high – Figure 6.28 Read Cycle, 16 Kbytes ROM MAD/ High Order Low Order (Addr driven by LSI53C876 Address Address Data driven by Memory) Valid Read Data MAS1/ (Driven by LSI53C876) MAS0/...
Page 285 MCE/low to MWE/ low – MWE/high to MCE/ high – – Figure 6.29 Write Cycle, 16 Kbytes ROM High Order Low Order Valid Write Data (Driven by LSI53C876) Address Address MAS1/ (Driven by LSI53C876) MAS0/ (Driven by LSI53C876) MCE/ (Driven by LSI53C876)
Page 286 6.4.2 PCI and External Memory Interface Timing Table 6.42 lists the PCI and External Memory Interface timing data. Table 6.42 LSI53C876 PCI and External Memory Interface Timing Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time –...
Page 287: Initiator Asynchronous Send
6.4.3 SCSI Interface Timing Table 6.43 through Table 6.49 Figure 6.30 through Figure 6.34 describe the LSI53C876 SCSI timing data. Table 6.43 Initiator Asynchronous Send Symbol Parameter Unit SACK/ asserted from SREQ/ asserted – SACK/ deasserted from SREQ/ deasserted –...
Page 288: Initiator Asynchronous Receive
Table 6.44 Initiator Asynchronous Receive Symbol Parameter Unit SACK/ asserted from SREQ/ asserted – SACK/ deasserted from SREQ/ deasserted – Data setup to SREQ/ asserted – Data hold from SACK/ asserted – Figure 6.31 Initiator Asynchronous Receive SREQ/ n + 1 SACK/ n + 1 SD[15:0]/,...
Page 289: Target Asynchronous Send
Table 6.45 Target Asynchronous Send Symbol Parameter Unit SREQ/ deasserted from SACK/ asserted – SREQ/ asserted from SACK/ deasserted – Data setup to SREQ/ asserted – Data hold from SACK/ asserted – Figure 6.32 Target Asynchronous Send SREQ/ n + 1 SACK/ n + 1 SD[15:0]/,...
Page 290 Figure 6.34 Initiator and Target Synchronous Transfers SREQ/ n + 1 or SACK/ Send Data Valid n Valid n + 1 SD[15:0]/, SDP[1:0]/ Receive Data SD[15:0]/, Valid n Valid n + 1 SDP[1:0]/ Table 6.47 SCSI-1 Transfers (SE, 5.0 Mbytes/s) Symbol Parameter Unit...
Page 291 Table 6.48 SCSI-2 Fast Transfers (10.0 Mbytes/s (8-Bit Transfers) or 20.0 Mbytes/s (16-Bit Transfers), 40 MHz Clock Symbol Parameter Unit Send SREQ/ or SACK/ assertion pulse width – Send SREQ/ or SACK/ deassertion pulse width – Receive SREQ/ or SACK/ assertion pulse width –...
Page 292 6.5 Package Diagrams Figure 6.35 is the 256-pin PBGA mechancial drawing and Figure 6.36 the 208-pin PQFP mechanical drawing for the LSI53C876. 6-60 Electrical Characteristics...
Page 293 Figure 6.35 256-pin PBGA (GU) Mechanical Drawing Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code GU. Package Diagrams...
Page 294 Figure 6.36 208-pin PQFP (P9) Mechanical Drawing (Sheet 1 of 2) Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code P9. 6-62...
Page 295 Figure 6.36 208-pin PQFP (P9) Mechanical Drawing (Sheet 2 of 2) Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code P9. Package Diagrams...
Page 296 6-64 Electrical Characteristics...
Page 297 Appendix A Register Summary Table A.1 lists the LSI53C876 conﬁguration registers by register name. Table A.1 Conﬁguration Registers Register Name Address Read/Write Page Base Address Register One (Memory) 0x14 Read/Write 4-10 Base Address Register Two (Memory) 0x18 Read/Write 4-10 Base Address Register Zero (I/O)
Page 298 4-12 Subsystem Vendor ID 0x2C Read Only 4-11 Vendor ID 0x00 Read Only Table A.2 lists the LSI53C876 SCSI registers by register name. Table A.2 SCSI Registers Register Name Address Read/Write Page Adder Sum Output (ADDER) 0x3C–0x3F Read Only 4-72...
Page 299 Table A.2 SCSI Registers (Cont.) Register Name Address Read/Write Page DMA FIFO (DFIFO) 0x20 Read/Write 4-58 DMA Interrupt Enable (DIEN) 0x39 Read/Write 4-69 DMA Mode (DMODE) 0x38 Read/Write 4-66 DMA Next Address (DNAD) 0x28–0x2B Read/Write 4-64 DMA SCRIPTS Pointer (DSP) 0x2C–0x2F Read/Write 4-64...
Page 300 Table A.2 SCSI Registers (Cont.) Register Name Address Read/Write Page SCSI First Byte Received (SFBR) 0x08 Read/Write 4-38 SCSI Input Data Latch (SIDL) 0x50–0x51 Read Only 4-94 SCSI Interrupt Enable One (SIEN1) 0x41 Read/Write 4-75 SCSI Interrupt Enable Zero (SIEN0) 0x40 Read/Write 4-73...
Page 301: Kbyte Interface With 200 Ns Memory
A[13:8] MAD3 4.7 K 27C128 LSI53C876 HCT374 MAS0/ HCT374 MAS1/ Notes: MAD bus sense logic enabled for 16 Kbytes of slow memory (200 ns device @ 33 MHz). MAD[3:1] pulled LOW internally. LSI53C876/876E PCI to Dual Channel SCSI Multifunction Controller...
Page 302: Kbyte Interface With 150 Ns Memory
A[7:0] MAD3 4.7 K 27C512-15/ A[15:8] 28F512-15/ Socket LSI53C876 HCT374 MAS0/ HCT374 MAS1/ Notes: MAD bus sense logic enabled for 64 Kbytes of fast memory (150 ns device @ 33 MHz). MAD3, MAD1, and MAD0 pulled LOW internally. External Memory Interface Diagram Examples...
Page 303: Kbyte Interface With 150 Ns Memory
A[7:0] MAD2 4.7 K 27C020-15/ A[15:8] 28F020-15/ Socket A[17:16] LSI53C876 HCT374 MAS0/ HCT374 MAS1/ HCT377 MAD[3:0] Bus Notes: MAD bus sense logic enabled for 256 Kbytes of fast memory (150 ns device @ 33 MHz). MAD[2:0] pulled LOW internally. The HCT374s may be replaced with HCT377s.
Page 304: Kbyte Interface With 150 Ns Memory
MOE/ D[7:0] MAD0 4.7 K MAD[7:0] A[7:0] MAD2 4.7 K A[15:8] LSI53C876 HCT374 MAS0/ HCT374 MAS1/ HCT377 MCE/ MAD[2:0] Bus HCT139 Note: MAD bus sense logic enabled for 512 Kbytes of slow memory (150 ns device, additional time required for HCT139 @ 33 MHz).
Page 305 4-58 4-62 arbitration arbitration in progress bit 4-45 arbitration mode bits 4-22 full arbitration 4-22 C_BE/[3:0] immediate arbitration bit 4-26 cache line size lost arbitration bit 4-45 (CLS[7:0]) LSI53C876/876E PCI to Dual Channel SCSI Multifunction Controller IX-1...
Page 306 cache line size enable bit 4-70 2-38 cache mode, see PCI cache mode 2-11 CTEST0 register 4-53 cap_ID (CID[7:0]) 4-16 CTEST1 register 4-54 capabilities pointer (CP[7:0]) 4-14 CTEST2 register 4-54 chained block move SCRIPTS instruction 2-42 CTEST4 register 4-59 chained block moves 2-40 CTEST5 register 4-61...
Page 307 electrical characteristics halt SCSI clock bit 4-93 AC characteristics 6-12 handshake-to-handshake timer bus activity enable bit 4-85 DC characteristics handshake-to-handshake timer expired bit 4-76 4-79 3.3 volt PCI handshake-to-handshake timer period bit 4-83 TolerANT technology hardware interrupts 2-33 enable parity checking 2-17 header type (HT[7:0]) enable parity checking bit...
Page 308 4-62 lost arbitration bit 4-45 chip test three 4-56 LSI53C700 family compatibility bit 4-72 chip test two 4-54 LSI53C876 benefits chip test zero 4-53 data structure address 4-49 DMA byte counter 4-63 DMA command 4-64 DMA control...
Page 309 operating registers (Cont.) 0x09 4-39 SCSI wide residue 4-81 0x0A 4-40 temporary stack 4-57 0x0B 4-41 0x0C 4-42 0x0D 4-44 0x0E 4-46 0x0F 4-48 0x10–0x13 4-49 parallel ROM interface 2-43 0x14 4-50 parity 2-17 0x18 4-53 parity error 0x19 4-54 parity error bit 4-78 0x1A...
Page 310 register bits (Cont.) lost arbitration 4-45 assert SCSI REQ/ signal 4-39 LSI53C700 family compatibility 4-72 assert SCSI RST/ signal 4-26 manual start mode 4-68 assert SCSI SEL/ signal 4-39 master control for set or reset pulses 4-61 burst disable 4-59 master data parity error 4-42 4-69...
Page 311 register bits (Cont.) SCRIPTS processor 2-13 source I/O-memory enable 4-67 instruction prefetching 2-14 SREQ/ status 4-41 internal RAM for instruction storage 2-14 SSEL/ status 4-41 performance 2-13 start DMA operation 4-71 SCRIPTS RAM 2-14 start SCSI transfer 4-27 SCSI start sequence 4-23 differential mode 2-24...
Page 312 SCSI serial EEPROM access 2-45 SODL most significant byte full bit 4-48 SCSI status one register 4-46 SODL register 4-95 SCSI status two register 4-48 SODR least significant byte full bit 4-44 SCSI status zero register 4-44 SODR most significant byte full bit 4-48 SCSI synchronous offset maximum 4-88...
Page 313 TP[2:0] 2-30 transfer control instructions 5-27 and SCRIPTS instruction prefetching 2-15 transfer rate synchronous 2-30 TRDY/ Ultra SCSI clock conversion factor bits 4-32 synchronous transfer period bits 4-34 Ultra SCSI enable bit 4-31 Ultra SCSI enable bit 4-31 Ultra SCSI synchronous data transfers 2-31 unexpected disconnect bit 4-74...
Page 314 IX-10 Index...
Page 315 Please include your name, phone number, fax number, and company address so that we may contact you directly for clariﬁcation or additional information. Thank you for your help in improving the quality of our documents. LSI53C876/876E PCI to Dual Channel SCSI Multifunction Controller...
Page 316 LSI Logic Corporation Technical Publications M/S E-198 Fax: 408.433.4333 Please tell us how you rate this document: LSI53C876/876E PCI to Dual Channel SCSI Multifunction Controller Technical Manual. Place a check mark in the appropriate blank for each category. Excellent Good Average...
Page 317 U.S. Distributors by State A. E. Avnet Electronics Colorado Indiana Minnesota http://www.hh.avnet.com Denver Fort Wayne Champlin B. M. Bell Microproducts, A. E. Tel: 303.790.1662 I. E. Tel: 219.436.4250 B. M. Tel: 800.557.2566 Inc. (for HAB’s) B. M. Tel: 303.846.3065 W. E. Tel: 888.358.9953 Eden Prairie http://www.bellmicro.com...
Page 318 U.S. Distributors by State (Continued) New York South Carolina Wisconsin Hauppauge A. E. Tel: 919.872.0712 Milwaukee I. E. Tel: 516.761.0960 W. E. Tel: 919.469.1502 A. E. Tel: 414.513.1500 Long Island W. E. Tel: 800.867.9953 South Dakota A. E. Tel: 516.434.7400 Wauwatosa A.
Page 319 Direct Sales Representatives by State (Component and Boards) E. A. Earle Associates Texas E. L. Electrodyne - UT Austin Group 2000 Tel: 512.794.9006 I. S. Inﬁnity Sales, Inc. Arlington ION Associates, Inc. Tel: 817.695.8000 R. A. Rathsburg Associ- Houston ates, Inc. Tel: 281.376.2000 Synergy Associates, Utah...
Page 320 Resource Centers LSI Logic Corporation Maryland INTERNATIONAL Taiwan Corporate Headquarters Bethesda Taipei Tel: 408.433.8000 Tel: 301.897.5800 France LSI Logic Asia, Inc. Fax: 408.433.8989 Fax: 301.897.8389 Paris Taiwan Branch LSI Logic S.A. Tel: 886.2.2718.7828 NORTH AMERICA Massachusetts Immeuble Europa Fax: 886.2.2718.8869 ♦...
Page 321 Fax: 86.10.6804.2521 Acal Nederland b.v. Tel: 31.40.2.502602 France Fax: 31.40.2.510255 Rungis Cedex Azzurri Technology France Switzerland Tel: 33.1.41806310 Brugg Fax: 33.1.41730340 LSI Logic Sulzer AG Tel: 41.32.3743232 Germany Fax: 41.32.3743233 Haar EBV Elektronik Taiwan Tel: 49.89.4600980 Taipei Fax: 49.89.46009840 Avnet-Mercuries...

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Lsi53c876e

LSI LSI53C876 Technical Manual

Chapter 1 General Description

Chapter 2 Functional Description

Chapter 3 Signal Descriptions

Chapter 4 Registers

Chapter 5 SCSI SCRIPTS Instruction Set

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