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LSI LSI53C895A Technical Manual

Pci to ultra2 scsi controller
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TECHNICAL
MANUAL
LSI53C895A
PCI to Ultra2
SCSI Controller
Version 2.2
A p r i l 2 0 0 1
®
S14028.B

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Summary of Contents for LSI LSI53C895A

  • Page 1 TECHNICAL MANUAL LSI53C895A PCI to Ultra2 SCSI Controller Version 2.2 A p r i l 2 0 0 1 ® S14028.B...
  • Page 2 LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties.
  • Page 3 Preface This book is the primary reference and technical manual for the LSI53C895A PCI to Ultra2 SCSI Controller. It contains a complete functional description for the product and also includes complete physical and electrical specifications. Audience This manual provides reference information on the LSI53C895A PCI to Ultra2 SCSI Controller.
  • Page 4 Summary, is a register summary. • Appendix B, External Memory Interface Diagram Examples, contains several example interface drawings for connecting the LSI53C895A to external ROMs. Related Publications For background information, please contact: ANSI 11 West 42nd Street New York, NY 10036 (212) 642-4900 Ask for document number X3.131-199X (SCSI-2)
  • Page 5 Preliminary version of the manual. 9/99 PCI timings corrected in Chapter 6, Table 6.3, and Figure 6.41 corrected. 2/00 Final version. 7/00 Added Figure 6.43. 4/01 All product names changed from SYM to LSI. Updated DC electrical specifications and test conditions. Preface...
  • Page 6 Preface...

  • Page 7: Table Of Contents

    Contents Chapter 1 General Description New Features in the LSI53C895A Benefits of Ultra2 SCSI Benefits of LVDlink ® TolerANT Technology LSI53C895A Benefits Summary 1.5.1 SCSI Performance 1.5.2 PCI Performance 1.5.3 Integration 1.5.4 Ease of Use 1.5.5 Flexibility 1.5.6 Reliability 1.5.7...
  • Page 8 2-62 2.6.4 Power State D3 2-62 Chapter 3 Signal Descriptions LSI53C895A Functional Signal Grouping Signal Descriptions 3.2.1 Internal Pull-ups on LSI53C895A Signals PCI Bus Interface Signals 3.3.1 System Signals 3.3.2 Address and Data Signals 3.3.3 Interface Control Signals 3.3.4 Arbitration Signals 3.3.5...
  • Page 9 Test Interface Signals 3-16 Power and Ground Signals 3-17 MAD Bus Programming 3-19 Chapter 4 Registers PCI Configuration Registers SCSI Registers 4-19 64-Bit SCRIPTS Selectors 4-104 Phase Mismatch Jump Registers 4-108 Chapter 5 SCSI SCRIPTS Instruction Set Low Level Register Interface Mode High Level SCSI SCRIPTS Mode 5.2.1 Sample Operation...
  • Page 10 Typical LSI53C895A Board Application LSI53C895A Block Diagram Parity Checking/Generation 2-29 DMA FIFO Sections 2-30 LSI53C895A Host Interface SCSI Data Paths 2-31 8-Bit HVD Wiring Diagram for Ultra2 SCSI 2-37 Regulated Termination for Ultra2 SCSI 2-39 Determining the Synchronous Transfer Rate...
  • Page 11 Rise and Fall Time Test Condition SCSI Input Filtering Hysteresis of SCSI Receivers 6-10 Input Current as a Function of Input Voltage 6-10 Output Current as a Function of Output Voltage 6-11 External Clock 6-12 Reset Input 6-13 6.10 Interrupt Output 6-14 6.11 PCI Configuration Register Read...
  • Page 12 6-59 6.39 Initiator and Target Synchronous Transfer 6-63 6.40 LSI53C895A 272-Pin BGA Top View 6-65 6.41 LSI53C895A 208-Pin Plastic Quad Flat Pack 6-68 6.42 LSI53C895A 208 PQFP Mechanical Drawing (Sheet 1 of 2) 6-74 6.43 LSI53C895A 272 PBGA Mechanical Drawing...
  • Page 13 3.14 Power and Ground Signals 3-17 3.15 Decode of MAD Pins 3-20 PCI Configuration Register Map SCSI Register Address Map 4-20 Examples of Synchronous Transfer Periods and Rates for SCSI-1 4-33 Example Transfer Periods and Rates for Fast SCSI-2, Ultra, and Ultra2 4-34 Maximum Synchronous Offset 4-35...
  • Page 14 6.15 External Clock 6-12 6.16 Reset Input 6-13 6.17 Interrupt Output 6-14 6.18 PCI Configuration Register Read 6-16 6.19 PCI Configuration Register Write 6-17 6.20 32-Bit Operating Register/SCRIPTS RAM Read 6-18 6.21 64-Bit Address Operating Register/SCRIPTS RAM Read 6-19 6.22 32-Bit Operating Register/SCRIPTS RAM Write 6-20 6.23...
  • Page 15 272 BGA Pin List by Location 6-66 6.52 BGA Pin List Alphabetically 6-67 6.53 Signal Names vs. Pin Number: 208-Pin Plastic Quad Flat Pack 6-69 6.54 LSI53C895A vs. LSI53C895 Pin/Ball Differences 6-72 LSI53C895A PCI Register Map LSI53C895A SCSI Register Map Contents...
  • Page 16 Contents...

  • Page 17: Chapter 1 General Description

    The LSI53C895A can be used as a drop-in replacement for the LSI53C895. The LSI53C895A has a local memory bus for local storage of the device’s BIOS ROM in flash memory or standard EEPROMs. The LSI53C895A supports programming of local flash memory for updates to BIOS.

  • Page 18: Typical Lsi53C895A System Application

    It implements multithreaded I/O algorithms with a minimum of processor intervention, solving the protocol overhead problems of previous intelligent and nonintelligent adapter designs. Figure 1.1 illustrates a typical LSI53C895A system and Figure 1.2 illustrates a typical LSI53C895A board application. Figure 1.1...

  • Page 19: New Features In The Lsi53C895A

    PCI Interface PCI Address, Data, Parity and Control Signals 1.1 New Features in the LSI53C895A The LSI53C895A is a drop-in replacement for the LSI53C895 PCI to Ultra2 SCSI Controller, with these additional benefits: • Supports 32-bit PCI Interface with 64-bit addressing.

  • Page 20: Benefits Of Ultra2 Scsi

    SCSI. When enabled, Ultra2 SCSI performs 40 megatransfers per second, resulting in approximately twice the synchronous transfer rates of Ultra SCSI. The LSI53C895A can perform 16-bit, Ultra2 SCSI synchronous transfers as fast as 80 Mbytes/s. This advantage is most noticeable in heavily loaded systems or with applications with large block requirements, such as video on-demand and image processing.

  • Page 21: Tolerant ® Technology

    LVDlink transceivers that can support LVD SCSI, SE, and HVD modes. The LVDlink technology also supports HVD signaling in legacy systems when external transceivers are connected to the LSI53C895A. This allows use of the LSI53C895A in both legacy and Ultra2 SCSI applications. ®...

  • Page 22: Lsi53C895A Benefits Summary

    1.5 LSI53C895A Benefits Summary This section of the chapter provides an overview of the LSI53C895A features and benefits. It contains these topics: • SCSI Performance • PCI Performance • Integration • Ease of Use • Flexibility • Reliability • Testability 1.5.1 SCSI Performance...

  • Page 23: Pci Performance

    I/O context switching. • Supports additional arithmetic capability with the Expanded Register Move instruction. 1.5.2 PCI Performance To improve PCI performance, the LSI53C895A: • Complies with PCI 2.2 specification. • Supports 32-bit 33 MHz PCI interface with 64-bit addressing. •...

  • Page 24: Integration

    1.5.3 Integration Features of the LSI53C895A which ease integration include: • High-performance SCSI core. • Integrated LVD transceivers. • Full 32-bit PCI DMA bus master. • Integrated SCRIPTS processor. • Memory-to-Memory Move instructions allow use as a third-party PCI bus DMA controller.

  • Page 25: Flexibility

    Ability to route system clock to SCSI clock. • Compatible with 3.3 V and 5 V PCI. 1.5.6 Reliability Enhanced reliability features of the LSI53C895A include: • 2 kV ESD protection on SCSI signals. • Protection against bus reflections due to impedance mismatches.

  • Page 26: Testability

    SCSI transfer rates. – Input signal filtering on SCSI receivers improves data integrity, even in noisy cabling environments. 1.5.7 Testability The LSI53C895A provides improved testability through: • Access to all SCSI signals through programmed I/O. • SCSI loopback diagnostics.

  • Page 27: Chapter 2 Functional Description

    Section 2.4, “Serial EEPROM Interface” • Section 2.5, “Alternative SSVID/SSID Loading Mechanism” • Section 2.6, “Power Management” The LSI53C895A PCI to Ultra2 SCSI Controller is composed of the following modules: • 32-bit PCI Interface with 64-bit addressing • PCI-to-Wide Ultra2 SCSI Controller •...

  • Page 28: Pci Functional Description

    Wide Ultra2 SCSI ROM/Flash 2-Wire Serial Memory EEPROM 2.1 PCI Functional Description The LSI53C895A implements a PCI-to-Wide Ultra2 SCSI controller. 2.1.1 PCI Addressing There are three physical PCI-defined address spaces: • PCI Configuration space. • I/O space for operating registers.
  • Page 29 AD[10:8] are reserved for multifunction devices. At initialization time, each PCI device is assigned a base address for I/O and memory accesses. In the case of the LSI53C895A, the upper 24 bits of the address are selected. On every access, the LSI53C895A compares its assigned base addresses with the value on the Address/Data bus during the PCI address phase.

  • Page 30: Pci Bus Commands And Functions Supported

    1. See the DMA Mode (DMODE) register. 2. See the Chip Test Three (CTEST3) register. 2.1.2.1 Interrupt Acknowledge Command The LSI53C895A does not respond to this command as a slave and it never generates this command as a master. Functional Description...
  • Page 31 2.1.2.2 Special Cycle Command The LSI53C895A does not respond to this command as a slave and it never generates this command as a master. 2.1.2.3 I/O Read Command The I/O Read command reads data from an agent mapped in I/O address space.
  • Page 32 This command is identical to the Memory Read command except that it additionally indicates that the master may intend to fetch more than one cache line before disconnecting. The LSI53C895A supports PCI Memory Read Multiple functionality and issues Memory Read Multiple commands on the PCI bus when the Read Multiple Mode is enabled.
  • Page 33 The Read Line function in the LSI53C895A takes advantage of the PCI 2.2 specification regarding issuing this command.
  • Page 34 4. The chip is aligned to a cache line boundary. When these conditions are met, the LSI53C895A issues a Memory Write and Invalidate command instead of a Memory Write command during all PCI write cycles.

  • Page 35: Pci Cache Mode

    Latency – In accordance with the PCI specification, the latency timer is ignored when issuing a Memory Write and Invalidate command such that when a latency time-out occurs, the LSI53C895A continues to transfer up to a cache line boundary. At that point, the chip relinquishes the bus, and finishes the transfer at a later time using another bus ownership.
  • Page 36 addresses corresponding to cache line boundaries. In conjunction with Cache Line Size register, the PCI commands Memory Read Line, Memory Read Multiple, Memory Write and Invalidate are each software enabled or disabled to allow the user full flexibility in using these commands.
  • Page 37 • To issue Memory Read Line commands, the Read Line enable bit in DMA Mode (DMODE) register must be set. • To issue Memory Read Multiple commands, the Read Multiple enable bit in the DMA Mode (DMODE) register must be set. •...
  • Page 38 • A single Memory Write to align to a cache boundary. • Multiple Memory Write and Invalidates. • A single data residual Memory Write to complete the transfer. Table 2.2 describes PCI cache mode alignment. 2-12 Functional Description...

  • Page 39: Pci Cache Mode Alignment

    Table 2.2 PCI Cache Mode Alignment Host Memory 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 PCI Functional Description 2-13...
  • Page 40 2.1.3.5 Examples: The examples in this section employ the following abbreviations: MR = Memory Read, MRL = Memory Read Line, MRM = Memory Read Multiple, MW = Memory Write, MWI = Memory Write and Invalidate. Read Example 1 – Burst = 4 Dwords, Cache Line Size = 4 Dwords: A to B: MRL (6 bytes) A to C:...
  • Page 41 Read Example 2 – Burst = 8 Dwords, Cache Line Size = 4 Dwords: A to B: MRL (6 bytes) A to C: MRL (13 bytes) A to D: MRM (17 bytes) C to D: MRM (5 bytes) C to E: MRM (21 bytes) D to F: MRM (31 bytes)
  • Page 42 Write Example 1 – Burst = 4 Dwords, Cache Line Size = 4 Dwords: A to B: MW (6 bytes) A to C: MW (13 bytes) A to D: MW (17 bytes) C to D: MW (5 bytes) C to E: MW (3 bytes) MWI (16 bytes) MW (2 bytes)
  • Page 43 Write Example 2 – Burst = 8 Dwords, Cache Line Size = 4 Dwords: A to B: MW (6 bytes) A to C: MW (13 bytes) A to D: MW (17 bytes) C to D: MW (5 bytes) C to E: MW (3 bytes) MWI (16 bytes) MW (2 bytes)

  • Page 44: Scsi Functional Description

    If the source and destination are not quad word aligned (that is, Source address [2:0] == Destination Address [2:0]), write aligning is not performed and Memory Write and Invalidate commands are not issued. The LSI53C895A is little endian only. 2.2 SCSI Functional Description The LSI53C895A provides an Ultra2 SCSI controller that supports an 8-bit or 16-bit bus.

  • Page 45: Scripts Processor

    The LSI53C895A offers low level register access or a high-level control interface. Like first generation SCSI devices, the LSI53C895A is accessed as a register-oriented device. Error recovery and/or diagnostic procedures use the ability to sample and/or assert any signal on the SCSI bus.

  • Page 46: Internal Scripts Ram

    2.2.2 Internal SCRIPTS RAM The LSI53C895A has 8 Kbyte (2048 x 32 bits) of internal, general purpose RAM. The RAM is designed for SCRIPTS program storage, but is not limited to this type of information. When the chip fetches SCRIPTS instructions or Table Indirect information from the internal RAM, these fetches remain internal to the chip and do not use the PCI bus.

  • Page 47: 64-Bit Addressing In Scripts

    Interrupt Status Zero (ISTAT0) is set anytime the LSI53C895A is connected to the SCSI bus either as an initiator or a target. This will happen after the LSI53C895A has successfully completed a selection or when it has successfully responded to a selection or reselection.

  • Page 48: Designing An Ultra2 Scsi System

    Ultra2 design. 2.2.5.1 Using the SCSI Clock Quadrupler The LSI53C895A can quadruple the frequency of a 40 MHz SCSI clock, allowing the system to perform Ultra2 SCSI transfers. This option is user selectable with bit settings in the...

  • Page 49: Prefetching Scripts Instructions

    Step 2. Poll bit 5 of the SCSI Test Four (STEST4) register. The LSI53C895A sets this bit as soon as it locks in the 160 MHz frequency. The frequency lockup takes approximately 100 microseconds. Step 3. Halt the SCSI clock by setting the Halt SCSI Clock bit...

  • Page 50: Opcode Fetch Burst Capability

    Setting the Burst Opcode Fetch Enable bit (bit 1) in the DMA Mode (DMODE) register (0x38) causes the LSI53C895A to burst in the first two Dwords of all instruction fetches. If the instruction is a Memory-to- Memory Move, the third Dword is accessed in a separate ownership. If the instruction is an indirect type, the additional Dword is accessed in a subsequent bus ownership.

  • Page 51: Jtag Boundary Scan Testing

    Chapter 5, “SCSI SCRIPTS Instruction Set.” 2.2.9 JTAG Boundary Scan Testing The LSI53C895A includes support for JTAG boundary scan testing in accordance with the IEEE 1149.1 specification with one exception, which is explained in this section. This device accepts all required boundary scan instructions including the optional CLAMP, HIGH-Z, and IDCODE instructions.

  • Page 52: Scsi Loopback Mode

    When the Loopback Enable bit is set in the SCSI Test Two (STEST2) register, bit 4, the LSI53C895A allows control of all SCSI signals whether the chip is operating in the initiator or target mode. For more information on this mode of operation refer to the LSI Logic SCSI SCRIPTS Processors Programming Guide.

  • Page 53: Bits Used For Parity Control And Generation

    Enable Zero interrupt when it detects a SCSI parity error. (SIEN0), Bit 0 Parity Error SCSI Interrupt This status bit is set whenever the LSI53C895A detects a Status Zero parity error on the SCSI bus. (SIST0), Bit 0 Status of SCSI...

  • Page 54: Scsi Parity Errors And Interrupts

    Table 2.4 SCSI Parity Control ASEP Description Does not check for parity errors. Parity is generated when sending SCSI data. Asserts odd parity when sending SCSI data. Does not check for parity errors. Parity is generated when sending SCSI data. Asserts even parity when sending SCSI data. Checks for odd parity on SCSI data received.

  • Page 55: Dma Fifo

    Figure 2.2 Parity Checking/Generation Asynchronous Asynchronous Synchronous Synchronous SCSI Send SCSI Receive SCSI Send SCSI Receive PCI Interface** PCI Interface** PCI Interface** PCI Interface** DMA FIFO* DMA FIFO* DMA FIFO* DMA FIFO* (64 bits X 118) (64 bits X 118) (64 bits X 118) (64 bits X 118) SCSI FIFO**...
  • Page 56 Byte Lane 1 Byte Lane 0 The LSI53C895A automatically supports misaligned DMA transfers. A 944-byte FIFO allows the LSI53C895A to support 2, 4, 8, 16, 32, 64, or 128 Dword bursts across the PCI bus interface. 2.2.12.1 Data Paths The data path through the LSI53C895A is dependent on whether data is being moved into or out of the chip, and whether SCSI data is being transferred asynchronously or synchronously.

  • Page 57: Lsi53C895A Host Interface Scsi Data Paths

    Figure 2.4 LSI53C895A Host Interface SCSI Data Paths Asynchronous Synchronous Synchronous Asynchronous SCSI Send SCSI Send SCSI Receive SCSI Receive PCI Interface** PCI Interface** PCI Interface** PCI Interface** DMA FIFO* DMA FIFO* DMA FIFO* DMA FIFO* (8 Bytes x 118)
  • Page 58 Byte Offset Counter, which consists of bits [1:0] in the CTEST5 register and bits [7:0] of the DMA FIFO register. AND the result with 0x3FF for a byte count between zero and 944. Step 2. Read bit 5 in the SCSI Status Zero (SSTAT0) SCSI Status Two (SSTAT2)
  • Page 59 accessible). If bit 6 is set in the SSTAT0 or SSTAT2 register, then the least significant byte or the most significant byte in the SODR register is full, respectively. Asynchronous SCSI Receive – Step 1. If the DMA FIFO size is set to 112 bytes (bit 5 of the Chip Test Five (CTEST5) register cleared), look at the...

  • Page 60: Scsi Bus Interface

    SCSI Wide Residue (SWIDE) register. 2.2.13 SCSI Bus Interface The LSI53C895A performs SE and LVD transfers, and supports traditional HVD operation when the chip is connected to external HVD transceivers. To support LVD SCSI, all SCSI data and control signals have both negative and positive signal lines.

  • Page 61: Hvd Signals

    MSG−, C_D−, I/O− and REQ−. DIFFSENS Input to the LSI53C895A used to detect the voltage level of a SCSI signal to determine whether it is a SE, LVD, or high-power differential signal. The encoded result is displayed in SCSI Test Four (STEST4) bits 7 and 6.
  • Page 62 The SCSI bidirectional control and data pins (SD[7:0] − SDP0 − , SREQ −,= SACK − , SMSG − , SI_O − , SC_D, and ATN − ) of the LSI53C895A connect to the bidirectional data pins (nA) of the SN75976A with a pull-up resistor.

  • Page 63: 8-Bit Hvd Wiring Diagram For Ultra2 Scsi

    Figure 2.5 8-Bit HVD Wiring Diagram for Ultra2 SCSI Schottky DIFFSENS Diode DIFFSENS (pin 21) LSI53C8XX 1.5 K SN75976A2 − SEL (42) CDE0 SEL+ 1.5 K (41) +SEL CDE1 1B − BSY+ − BSY (34) CDE2 RST+ (33) +BSY 2B − −...
  • Page 64 For information on terminators that support LVD, refer to the SPI-3 draft standard. Note: If the LSI53C895A is to be used in a design that has only an 8-bit SCSI bus, all 16 data lines must still be terminated. 2-38...

  • Page 65: Select/Reselect During Selection/Reselection

    (SCSI Chip ID (SCID) bits 5 and 6, respectively) should both be asserted so that the LSI53C895A may respond as an initiator or as a target. If only selection is enabled, the LSI53C895A cannot be reselected as an initiator. There are also status and interrupt bits in the...

  • Page 66: Synchronous Operation

    CPU before SCRIPTS execution begins, from within SCRIPTS using a Table Indirect I/O instruction, or with a Read-Modify-Write instruction. The LSI53C895A can receive data from the SCSI bus at a synchronous transfer period as short as 25 ns, regardless of the transfer period used to send data.

  • Page 67: Determining The Synchronous Transfer Rate

    Figure 2.7 Determining the Synchronous Transfer Rate SCF2 SCF1 SCF0 XFERP Divisor Divisor This point must not Divide by 4 Receive exceed Clock 160 MHz Synchronous Send Clock Divider Divider (to SCSI Bus) Clock SCLK QCLK Quadrupler Asynchronous Divider SCSI Logic CCF2 CCF1 CCF0...
  • Page 68 25 ns, which is half the 50 ns period allowed under Ultra SCSI. This will allow a maximum transfer rate of 80 Mbytes/s on a 16-bit, LVD SCSI bus. The LSI53C895A has a SCSI clock quadrupler that must be enabled for the chip to perform Ultra2 SCSI transfers with a 40 MHz oscillator.

  • Page 69: Interrupt Handling

    A hybrid approach would use hardware interrupts for long waits, and use polling for short waits. 2.2.16.2 Registers The registers in the LSI53C895A that are used for detecting or defining interrupts are Interrupt Status Zero (ISTAT0),...
  • Page 70 DMA FIFO to memory before generating the interrupt. If the LSI53C895A is sending data to the SCSI bus and a fatal SCSI interrupt condition occurs, data could be left in the DMA FIFO. Because...
  • Page 71 (SIST0) SCSI Interrupt Status One (SIST1) being set) are nonfatal. When the LSI53C895A is operating in the Initiator mode, only the Function Complete (CMP), Selected (SEL), Reselected (RSL), General Purpose Timer Expired (GEN), and Handshake-to-Handshake Timer Expired (HTH) interrupts are nonfatal.
  • Page 72 CPU. This prevents an interrupt when arbitration is complete (CMP set), when the LSI53C895A is selected or reselected (SEL or RSL set), when the initiator asserts ATN (target mode: SATN/ active), or when the General Purpose or Handshake-to-Handshake timers expire.
  • Page 73 IRQ/. 2.2.16.5 Stacked Interrupts The LSI53C895A will stack interrupts if they occur one after the other. If the SIP or DIP bits in the ISTAT register are set (first level), then there is already at least one pending interrupt, and any future interrupts are...
  • Page 74 These ‘locked out’ SCSI interrupts are posted as soon as the DMA FIFO is empty. 2.2.16.6 Halting in an Orderly Fashion When an interrupt occurs, the LSI53C895A attempts to halt in an orderly fashion. • If the interrupt occurs in the middle of an instruction fetch, the fetch is completed, except in the case of a Bus Fault.
  • Page 75 2.2.16.7 Sample Interrupt Service Routine The following is a sample of an interrupt service routine for the LSI53C895A. It can be repeated during polling or should be called when the IRQ/ pin is asserted during hardware interrupts. 1. Read Interrupt Status Zero (ISTAT0).

  • Page 76: Interrupt Routing

    2.2.17 Interrupt Routing This section documents the recommended approach to RAID ready interrupt routing for the LSI53C895A. In order to be compatible with AMI RAID upgrade products and the LSI53C895A, the following requirements must be met: • When a RAID upgrade card is installed in the upgrade slot, interrupts...

  • Page 77: Chained Block Moves

    The first option is to have the LSI53C895A load its PCI Subsystem ID using a serial EPROM on power-up. If bit 15 in this ID is set, the LSI Logic BIOS and operating system drivers (not all versions support this capability) will ignore the chip. This makes it possible to control the assignment of the mainboard SCSI controller using a configuration utility.
  • Page 78 Figure 2.8 Block Move and Chained Block Move Instructions Host Memory SCSI Bus 0x03 0x02 0x01 0x00 0x04 0x03 0x06 0x05 0x07 0x06 0x05 0x04 0x0B 0x0A 0x09 0x08 0x0F 0x0E 0x0D 0x0C 0x09 0x07 0x13 0x12 0x11 0x10 0x0B 0x0A 0x0D 0x0C...
  • Page 79 (this flag is not set if a normal Block Move instruction is used). Under this condition, the SCSI controller does not send the low-order byte of the last partial memory transfer across the SCSI bus. Instead, the low-order byte is temporarily stored in the lower byte of the SCSI Output Data Latch (SODL) register and the WSS flag is set.
  • Page 80 2.2.18.4 SODL Register For send data, the low-order byte of the SCSI Output Data Latch (SODL) register holds the low-order byte of a partial memory transfer which has not yet been transferred across the SCSI bus. This stored data is usually “married”...

  • Page 81: Parallel Rom Interface

    Chained Block Moves. 2.3 Parallel ROM Interface The LSI53C895A supports up to one megabyte of external memory in binary increments from 16 Kbytes, to allow the use of expansion ROM for add-in PCI cards. This interface is designed for low speed operations such as downloading instruction code from ROM;...

  • Page 82: Parallel Rom Support

    MAD[3:1] should be pulled HIGH. Note: There are internal pull-downs on all of the MAD bus signals. The LSI53C895A allows the system to determine the size of the available external memory using the Expansion ROM Base Address register in the PCI configuration space.

  • Page 83: Serial Eeprom Interface

    2.4 Serial EEPROM Interface The LSI53C895A implements an interface that allows attachment of a serial EEPROM device to the GPIO0 and GPIO1 pins. There are two modes of operation relating to the serial EEPROM and the Subsystem ID and Subsystem Vendor ID registers. These modes are programmable through the MAD7 pin which is sampled at power-up.

  • Page 84: No Download Mode

    Subsystem ID Subsystem Vendor ID registers can be accomplished in the LSI53C895A without the use of a serial EEPROM. This alternative loading mechanism is the only way to set the SSVID/SSID registers to something other than the default value, except through Serial EEPROM download.
  • Page 85 An additional register, the Subsystem ID Access, is located in the PCI configuration space at offset 0x48–0x4B. This is a 32-bit write only register that always reads back a value of 0x00000000. Once enabled and unlocked using a write of three specific byte values to offset 0x48, a write to this register is shadowed into the PCI Subsystem register at offset 0x2C.

  • Page 86: Power Management

    The write of the subsystem value in Step 5. 2.6 Power Management The LSI53C895A complies with the PCI Bus Power Management Interface Specification, Revision 1.1. The PCI Function Power States D0, D1, D2, and D3 are defined in that specification.

  • Page 87: Power State D0

    Power state D1 is a lower power state than D0. In this state, the LSI53C895A core is placed in the snooze mode and the SCSI CLK is disabled. In the snooze mode, a SCSI reset does not generate an IRQ/ signal.

  • Page 88: Power State D2

    2.6.3 Power State D2 Power state D2 is a lower power state than D1. In this state the LSI53C895A core is placed in the coma mode. The following PCI Configuration Space command register enable bits are suppressed: • I/O Space Enable •...

  • Page 89: Chapter 3 Signal Descriptions

    Signal Descriptions This chapter presents the LSI53C895A pin configuration and signal definitions using tables and illustrations. The LSI53C895A comes in a 208 PQFP and a 272 BGA package. Definitions in the signal description tables are for both the 208 PQFP and the 272 BGA. This chapter contains the following sections: •...

  • Page 90: Lsi53C895A Functional Signal Grouping

    3.1 LSI53C895A Functional Signal Grouping Figure 3.1 presents the LSI53C895A signals by functional group. Figure 3.1 LSI53C895A Functional Signal Grouping LSI53C895A System RST/ SCLK Address AD[31:0] SD[15:0] C_BE[3:0] SDP[1:0] Data DIFFSENS FRAME/ TRDY/ SCSI IRDY/ Interface SCD/ STOP/ Control SIO/...

  • Page 91: Signal Descriptions

    Sustained 3-state, an active LOW 3-state signal owned and driven by one and only one agent at a time. 3.2.1 Internal Pull-ups on LSI53C895A Signals Several signals in the LSI53C895A have internal pull-up resistors. Table 3.1 describes the conditions that enable these pull-ups.

  • Page 92: Pci Bus Interface Signals

    3.3 PCI Bus Interface Signals The PCI Bus Interface Signals section contains tables describing the signals for the following signal groups: System Signals, Address and Data Signals, Interface Control Signals, Arbitration Signals, Error Reporting Signals, Interrupt Signals, and SCSI GPIO Signals.

  • Page 93: Address And Data Signals

    3.3.2 Address and Data Signals Table 3.3 describes Address and Data signals. Table 3.3 Address and Data Signals Name PQFP BGA Pos Type Strength Description AD[31:0] 199, 201–204, U2, V1, V2, 8 mA PCI Physical Dword Address 3, 5, 6, 10–12, W1, V3, Y3, V5, and Data are multiplexed on 14–17, 19,...

  • Page 94: Interface Control Signals

    Table 3.3 Address and Data Signals (Cont.) Name PQFP BGA Pos Type Strength Description 8 mA PCI Parity is the even parity bit that protects the AD[31:0] and C_BE[3:0]/ lines. During the address phase, both the address and command bits are covered.
  • Page 95 Table 3.4 Interface Control Signals (Cont.) Name PQFP BGA Pos Type Strength Description IRDY/ S/T/S 8 mA PCI Initiator Ready indicates the initiating agent’s (bus master’s) ability to complete the current data phase of the transaction. IRDY/ is used with TRDY/. A data phase is completed on any clock when both IRDY/ and TRDY/ are sampled asserted.

  • Page 96: Arbitration Signals

    3.3.4 Arbitration Signals Table 3.5 describes Arbitration signals. Table 3.5 Arbitration Signals Name PQFP BGA Pos Type Strength Description REQ/ 8 mA PCI Request indicates to the system arbiter that this agent desires use of the PCI bus. This is a point-to-point signal.

  • Page 97: Interrupt Signals

    3.3.6 Interrupt Signals Table 3.7 describes the Interrupt signals. Table 3.7 Interrupt Signals Name PQFP BGA Pos Type Strength Description IRQ/ 8 mA PCI Interrupt Request. This signal, when asserted LOW, indicates that an interrupting condition has occurred and that service is required from the host CPU.

  • Page 98: Scsi Gpio Signals

    MAD7 pin to serve as the data signal for the serial EEPROM interface. This signal can also be programmed to be driven LOW when the LSI53C895A is active on the SCSI bus. GPIO1_ 8 mA SCSI General Purpose I/O pin.

  • Page 99: Scsi Bus Interface Signals

    3.4 SCSI Bus Interface Signals The SCSI Bus Interface signals section contains tables describing the signals for the following signal groups: SCSI Bus Interface Signals, SCSI Signals, SCSI Control Signals. 3.4.1 SCSI Bus Interface Signal Table 3.9 describes the SCSI Bus Interface signal. Table 3.9 SCSI Bus Interface Signal Name...

  • Page 100: Scsi Signals

    DIFFSENS signal on the physical SCSI bus. LVD Mode: When a voltage between 0.7 V and 1.9 V is present on this pin, the LSI53C895A will operate in the LVD mode. SE Mode: When this pin is driven LOW (below 0.5 V) indicating SE bus operation, the LSI53C895A will operate in the SE mode.

  • Page 101: Scsi Control Signals

    3.4.3 SCSI Control Signals Table 3.11 describes the SCSI Control signals. Table 3.11 SCSI Control Signals Name PQFP BGA Pos Type Strength Description SCSI Control includes the following signals: SCD− 48 mA SCSI phase line, command/data. SCD+ SCSI SIO− SCSI phase line, input/output. SIO+ SMSG−...

  • Page 102: Flash Rom And Memory Interface Signals

    Memory Output Enable. This pin is used as an output enable signal to an external EEPROM or flash memory during read operations. It is also used to test the connectivity of the LSI53C895A signals in test mode. MAC/_ 16 mA Memory Access Control. This pin...
  • Page 103 (bits [15:8]) of an external EEPROM or flash memory. Since the LSI53C895A moves addresses eight bits at a time, this pin connects to the clock of an external bank of flip-flops which assemble up to a 20-bit address for the external memory.

  • Page 104: Test Interface Signals

    Test Interface Signals Name PQFP BGA Pos Type Strength Description TEST_HSC/ 82 Test Halt SCSI Clock. For LSI Logic pulled HIGH internally. This signal can also cause a full chip reset. Test Clock. This pin provides the clock for the JTAG test logic.

  • Page 105: Power And Ground Signals

    3.7 Power and Ground Signals Table 3.14 describes the Power and Ground signals. Table 3.14 Power and Ground Signals Name PQFP BGA Pos Type Strength Description VSS_I/O 8, 18, 31, 41, A1, D4, D8, Ground for PCI bus 56, 78, 91, D13, D17, H4, drivers/receivers, SCSI bus 110, 120, 128,...
  • Page 106 Table 3.14 Power and Ground Signals (Cont.) Name PQFP BGA Pos Type Strength Description 4, 49, 53, 62, A2, A6, These pins have NO internal 103–109, A19–A20, B1, connection. 152–159, 177, B11, B17–18, 192, 207, 208 C2–9, C11–16, C18, D5, D7, D9–10, D12, D14, E2–4, E18, F18,...
  • Page 107 3.8 MAD Bus Programming The MAD[7:0] pins, in addition to serving as the address/data bus for the local memory interface, also are used to program power-up options for the chip. A particular option is programmed allowing the internal pull-down current sink to pull the pin LOW at reset or by connecting a 4.7 k Ω...

  • Page 108: Decode Of Mad Pins

    • MAD[3:1] – These pins are used to set the size of the external expansion ROM device attached. Encoding for these pins are listed Table 3.15 (“0” indicates a pull-down resistor is attached, “1” indicates a pull-up resistor is attached). Table 3.15 Decode of MAD Pins MAD[3:1]...

  • Page 109: Pci Configuration Registers

    Chapter 4 Registers This chapter describes all LSI53C895A registers and is divided into the following sections: • Section 4.1 “PCI Configuration Registers” • Section 4.2 “SCSI Registers” • Section 4.3 “64-Bit SCRIPTS Selectors” • Section 4.4 “Phase Mismatch Jump Registers”...

  • Page 110: Pci Configuration Register Map

    Only those registers and bits that are currently supported by the LSI53C895A are described in this chapter. Reserved bits should not be accessed Table 4.1 PCI Configuration Register Map...
  • Page 111 PCI cycles. When a zero is written to this register, the LSI53C895A is logically disconnected from the PCI bus for all accesses except configuration accesses. PCI Configuration Registers...
  • Page 112 Write and Invalidate commands. Reserved Enable Bus Mastering This bit controls the ability of the LSI53C895A to act as a master on the PCI bus. A value of zero disables this device from generating PCI bus master accesses. A value of one allows the LSI53C895A to behave as a bus master.
  • Page 113 This bit controls the LSI53C895A response to I/O space accesses. A value of zero disables the device response. A value of one allows the LSI53C895A to respond to I/O Space accesses at the address range specified by the Base Address Register Zero (I/O) register in the PCI configuration space.
  • Page 114 These bits are read only and should indicate the slowest time that a device asserts DEVSEL/ for any bus command except Configuration Read and Configuration Write. The LSI53C895A supports a value of 0b01. Data Parity Error Reported This bit is set when all of the following conditions are met: •...
  • Page 115 Register: 0x08 Revision ID (Rev ID) Read Only Revision ID [7:0] This register contains the current revision level of the device. Registers: 0x09–0x0B Class Code Read Only Class Code [23:0] This 24-bit register is used to identify the generic function of the device.
  • Page 116 The Latency Timer register specifies, in units of PCI bus clocks, the value of the Latency Timer for this PCI bus master. The LSI53C895A supports this timer. All eight bits are writable, allowing latency values of 0–255 PCI clocks. Use the following equation to calculate an optimum latency value for the LSI53C895A.
  • Page 117 [31:0] This base address register is used to map the operating register set into I/O space. The LSI53C895A requires 256 bytes of I/O space for this base address register. It has bit zero hardwired to one. Bit 1 is reserved and returns a zero on all reads, and the other bits are used to map the device into I/O space.
  • Page 118 This base register is used to map the SCRIPTS RAM into memory space. The default value of this register is 0x00000000. The LSI53C895A points to 8192 bytes of address space with this register. This register has bits [12:0] hardwired to 0b0000000000000. For detailed information on the operation of this register, refer to the PCI 2.2 specification.
  • Page 119 If the external serial EEPROM interface is disabled (MAD[7] HIGH), this register returns a value of 0x1000 (LSI Logic Vendor ID). The 16-bit value that should be stored in the external serial EEPROM for this register is the vendor’s PCI Vendor ID and must be obtained from the PCI Special Interest Group (SIG).
  • Page 120 If the external serial EEPROM interface is enabled (MAD[7] is LOW), this register is automatically loaded at power-up from the external serial EEPROM and will contain the value downloaded from the serial EEPROM or a value of 0x0000 if the download fails. If the external serial EEPROM is disabled (MAD[7] pulled HIGH), the register returns a value of 0x1000.
  • Page 121 Expansion ROM Base Address register with all ones and then reading back the register. The LSI53C895A responds with zeros in all don’t care locations. The ones in the remaining bits represent the binary version of the external memory size. For example,...
  • Page 122 This register is used to specify the desired settings for latency timer values. Min_Gnt is used to specify how long a burst period the device needs. The value specified in this register is in units of 0.25 microseconds. The LSI53C895A sets this register to 0x11. 4-14 Registers...
  • Page 123 Max_Lat is used to specify how often the device needs to gain access to the PCI bus. The value specified in this register is in units of 0.25 microseconds. The LSI53C895A sets this register to 0x40. Register: 0x40...
  • Page 124 [15:11] Bits [15:11] define the power management states in which the LSI53C895A will assert the PME pin. These bits are all set to zero because the LSI53C895A does not provide a PME signal. D2_Support The LSI53C895A sets this bit to indicate support for power management state D2.
  • Page 125 DSLT Data_Select [12:9] The LSI53C895A does not support the data register. Therefore, these four bits are always cleared. PME_Enable The LSI53C895A always returns a zero for this bit to indicate that PME assertion is disabled. Reserved [7:2] PWS[1:0] Power State...
  • Page 126 Read Only DATA DATA Data [7:0] This register provides an optional mechanism for the function to report state-dependent operating data. The LSI53C895A does not use this register and always returns 0x00. Registers: 0x48–0x4B Subsystem ID Access Write Only SIDA SIDA...
  • Page 127 PCI bus using Memory or I/O mapping. The address map of the SCSI registers is shown in Table 4.2. Note: The only registers that the host CPU can access while the LSI53C895A is executing SCRIPTS are the Interrupt Status Zero (ISTAT0), Interrupt Status One (ISTAT1) Mailbox Zero...

  • Page 128: Scsi Register Address Map

    Table 4.2 SCSI Register Address Map 16 15 SCNTL3 SCNTL2 SCNTL1 SCNTL0 0x00 GPREG0 SDID SXFER SCID 0x04 SBCL SSID SOCL SFBR 0x08 SSTAT2 SSTAT1 SSTAT0 DSTAT 0x0C 0x10 MBOX1 MBOX0 ISTAT1 ISTAT0 0x14 CTEST3 CTEST2 CTEST1 CTEST0 0x18 TEMP 0x1C CTEST6 CTEST5...
  • Page 129 Simple arbitration Reserved Reserved Full arbitration, selection/reselection Simple Arbitration 1. The LSI53C895A waits for a bus free condition to occur. 2. It asserts SBSY/ and its SCSI ID (contained in the SCSI Chip ID (SCID) register) onto the SCSI bus. If...
  • Page 130 SCSI bus. 3. If the SSEL/ signal is asserted by another SCSI device or if the LSI53C895A detects a higher priority ID, the LSI53C895A deasserts SBSY, deasserts its ID, and waits until the next bus free state to try arbitration again.
  • Page 131 WATN Select with SATN/ on a Start Sequence When this bit is set and the LSI53C895A is in the initiator mode, the SATN/ signal is asserted during selection of a SCSI target device. This is to inform the target that the LSI53C895A has a message to send.
  • Page 132 Setting this bit only affects SCSI send operations. Assert SCSI Data Bus When this bit is set, the LSI53C895A drives the contents of the SCSI Output Data Latch (SODL) register onto the SCSI data bus.
  • Page 133 If the LSI53C895A is receiving data, any data residing in the DMA FIFO is sent to memory before halting. When this bit is set, the LSI53C895A does not halt the SCSI transfer when SATN/ or a parity error is received. Connected This bit is automatically set any time the LSI53C895A is connected to the SCSI bus as an initiator or as a target.
  • Page 134 Arbitration is retried until won. At that point, the LSI53C895A holds SBSY and SSEL asserted, and waits for a select or reselect sequence. The Immediate Arbitration bit is cleared automatically when the selection or reselection sequence is completed, or times out.
  • Page 135 Using chained mode facilitates partial receive transfers and allows correct partial send behavior. When this bit is set and a data transfer ends on an odd byte boundary, the LSI53C895A stores the last byte in SCSI Wide Residue (SWIDE) register during a...

  • Page 136: Block Move Instruction

    (SODL) register during a send operation. This byte is combined with the first byte from the subsequent transfer so that a wide transfer is completed. SLPMD SLPAR Mode If this bit is cleared, the SCSI Longitudinal Parity (SLPAR) register functions as a byte-wide longitudinal parity register.
  • Page 137 Setting this bit enables Ultra SCSI or Ultra2 SCSI synchronous transfers. The default value of this bit is 0. This bit should remain cleared if the LSI53C895A is not operating in Ultra SCSI mode or faster. When this bit is set, the signal filtering period for SREQ/...
  • Page 138 Note: Set this bit to achieve Ultra SCSI transfer rates in legacy systems that use an 80 MHz clock. SCF[2:0] Synchronous Clock Conversion Factor [6:4] These bits select a factor by which the frequency of SCLK is divided before being presented to the synchronous SCSI control logic.
  • Page 139 Enable Response to Selection When this bit is set, the LSI53C895A is able to respond to bus-initiated selection at the chip ID in the RESPID0 and RESPID1 registers. Note that the chip does not automatically reconfigure itself to target mode as a result of being selected.
  • Page 140 The synchronous transfer period the LSI53C895A should use when transferring SCSI data is determined in the following example: The LSI53C895A is connected to a hard disk which can transfer data at 10 Mbytes/s synchronously. The LSI53C895A’s SCLK is running at 40 MHz. The...

  • Page 141: Examples Of Synchronous Transfer Periods And Rates

    (This SCSI synchronous core clock is determined in SCNTL3 bits [6:4], ExtCC = 1 if SCNTL1 bit 7 is asserted and the LSI53C895A is sending data. ExtCC = 0 if the LSI53C895A is receiving data.) SXFERP = 100 ÷ 25 = 4...

  • Page 142: Ultra, And Ultra2

    4.17 MO[4:0] Max SCSI Synchronous Offset [4:0] These bits describe the maximum SCSI synchronous offset used by the LSI53C895A when transferring synchronous SCSI data in either the initiator or target mode. Table 4.5 describes the possible combinations and their relationship to the synchronous data offset used by the LSI53C895A.

  • Page 143: Maximum Synchronous Offset

    Table 4.5 Maximum Synchronous Offset Synchronous Offset 0-Asynchronous SCSI Registers 4-35...
  • Page 144 Register: 0x06 SCSI Destination ID (SDID) Read/Write Reserved [7:4] Encoded Destination SCSI ID [3:0] Writing these bits set the SCSI ID of the intended initiator or target during SCSI reselection or selection phases, respectively. When executing SCRIPTS, the SCRIPTS processor writes the destination SCSI ID to this register. The SCSI ID is defined by the user in a SCRIPTS Select or Reselect instruction.
  • Page 145 Move. However, it can be loaded using SCRIPTS Read/Write operations. To load the SFBR with a byte stored in system memory, the byte must first be moved to an intermediate LSI53C895A register (such as a SCRATCH register), and then to the SFBR.
  • Page 146 It is controlled by the SCRIPTS processor when executing SCSI SCRIPTS. SOCL is used only when transferring data using programmed I/O. Some bits are set (1) or cleared (0) when executing SCSI SCRIPTS. Do not write to the register once the LSI53C895A starts executing normal SCSI SCRIPTS. 4-38...
  • Page 147 Encoded Destination SCSI ID [3:0] Reading the SSID register immediately after the LSI53C895A is selected or reselected returns the binary-encoded SCSI ID of the device that performed the operation. These bits are invalid for targets that are selected under the single initiator option of the SCSI-1 specification.
  • Page 148 Reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register in case additional interrupts are pending (the LSI53C895A stacks interrupts). The DIP bit in the Interrupt Status Zero (ISTAT0) register is also cleared.
  • Page 149 MDPE Master Data Parity Error This bit is set when the LSI53C895A as a master detects a data parity error, or a target device signals a parity error during a data phase. This bit is completely disabled by the Master Parity Error Enable bit (bit 3 of Chip Test Four (CTEST4)).
  • Page 150 Data (bit 18) and Compare Phase (bit 17) bits are set in the DMA Byte Counter (DBC) register while the LSI53C895A is in target mode. • During a Transfer Control instruction, the Carry Test bit (bit 21) is set and either the Compare Data (bit 18) or Compare Phase (bit 17) bit is set.
  • Page 151 Register: 0x0D SCSI Status Zero (SSTAT0) Read Only SDP0 SIDL Least Significant Byte Full This bit is set when the least significant byte in the SCSI Input Data Latch (SIDL) register contains data. Data is transferred from the SCSI bus to the SCSI Input Data Latch register before being sent to the DMA FIFO and then to the host bus.
  • Page 152 Arbitration in Progress Arbitration in Progress (AIP = 1) indicates that the LSI53C895A has detected a Bus Free condition, asserted SBSY, and asserted its SCSI ID onto the SCSI bus. Lost Arbitration When set, LOA indicates that the LSI53C895A has...

  • Page 153: Scsi Synchronous Data Fifo Word Count

    SCSI FIFO can hold up to 31 bytes for narrow SCSI synchronous data transfers, or up to 31 words for wide. Values over 31 will not occur. Table 4.6 SCSI Synchronous Data FIFO Word Count Bytes or Words in the (SSTAT2 bit 4) SCSI FIFO SCSI Registers...
  • Page 154 SDP0L Latched SCSI Parity This bit reflects the SCSI parity signal (SDP0/), corresponding to the data latched in the SCSI Input Data Latch (SIDL). It changes when a new byte is latched into the least significant byte of the SIDL register. This bit is active HIGH, in other words, it is set when the parity signal is active.
  • Page 155 SCSI device selects or reselects the LSI53C895A. If the Connected bit is asserted and the LDSC bit is asserted, a disconnect is indicated. This bit is set when the Connected bit in SCNTL1 is off. This bit is cleared when a Block Move instruction is executed while the Connected bit in SCNTL1 is on.
  • Page 156 SRST SIGP INTF This register is accessible by the host CPU while a LSI53C895A is executing SCRIPTS (without interfering in the operation of the function). It is used to poll for interrupts if hardware interrupts are disabled. Read this register after servicing an interrupt to check for stacked interrupts.

  • Page 157: Scripts Instructions

    SRST Software Reset Setting this bit resets the LSI53C895A. All operating registers are cleared to their respective default values and all SCSI signals are deasserted. Setting this bit does not assert the SCSI RST/ signal. This reset does not clear the ID Mode bit or any of the PCI configuration registers.
  • Page 158 LSI53C895A responds to a bus-initiated selection or reselection. It is also set after the LSI53C895A wins arbitration when operating in low level mode. When this bit is clear, the LSI53C895A is not connected to the SCSI bus. INTF Interrupt-on-the-Fly This bit is asserted by an INTFLY instruction during SCRIPTS execution.
  • Page 159 SCSI Interrupt Status One (SIST1) registers. DMA Interrupt Pending This status bit is set when an interrupt condition is detected in the DMA portion of the LSI53C895A. The following conditions cause a DMA interrupt to occur: • A PCI parity error is detected •...
  • Page 160 Register: 0x15 Interrupt Status One (ISTAT1) Read/Write FLSH SRUN Reserved [7:3] FLSH Flushing Reading this bit monitors if the chip is currently flushing data. If set, the chip is flushing data from the DMA FIFO. If cleared, no flushing is occurring. This bit is read only and writes will have no effect on the value of this bit.
  • Page 161 Register: 0x16 Mailbox Zero (MBOX0) Read/Write MBOX0 MBOX0 Mailbox Zero [7:0] These are general purpose bits that may be read or written while SCRIPTS are running. They also may be read or written by the SCRIPTS processor. Note: The host and the SCRIPTS processor code could potentially attempt to access the same mailbox byte at the same time.
  • Page 162 Register: 0x18 Chip Test Zero (CTEST0) Read/Write Byte Empty in DMA FIFO [7:0] These bits identify the bottom bytes in the DMA FIFO that are empty. Each bit corresponds to a byte lane in the DMA FIFO. For example, if byte lane three is empty, then FMT3 will be set.
  • Page 163 Register: 0x1A Chip Test Two (CTEST2) Read Only (bit 3 write) DDIR SIGP PCICIE TEOP DREQ DACK DDIR Data Transfer Direction This status bit indicates which direction data is being transferred. When this bit is set, the data is transferred from the SCSI bus to the host bus.
  • Page 164 TEOP SCSI True End of Process This bit indicates the status of the LSI53C895A’s TEOP signal. The TEOP signal acknowledges the completion of a transfer through the SCSI portion of the LSI53C895A. When this bit is set, TEOP is active. When this bit is clear, TEOP is inactive.
  • Page 165 Chip Test Five (CTEST5) register, determines the direction of the transfer. This bit is not self-clearing; clear it once the data is successfully transferred by the LSI53C895A. Note: Polling of FIFO flags is allowed during flush operations. Clear DMA FIFO When this bit is set, all data pointers for the DMA FIFO are cleared.
  • Page 166 Return instruction is executed. This address points to the next instruction to execute. Do not write to this register while the LSI53C895A is executing SCRIPTS. During any Memory-to-Memory Move operation, the contents of this register are preserved. The power-up value of this register is indeterminate.
  • Page 167 Once the chip has stopped transferring data, these bits are stable. DMA FIFO (DFIFO) register counts the number of bytes transferred between the DMA core and the SCSI core. The DMA Byte Counter (DBC) register counts the number of bytes transferred across the host bus. The difference between these two counters represents the number of bytes remaining in the DMA FIFO.
  • Page 168 This bit is used with FBL[2:0]. See Bits [2:0] description in this register. SCSI Data High Impedance Setting this bit causes the LSI53C895A to place the SCSI data bus SD[15:0] and the parity lines SDP[1:0] in a high impedance state. In order to transfer data on the SCSI bus, clear this bit.
  • Page 169 LSI53C895A is informed of the error by the PERR/ pin being asserted by the target. When this bit is cleared, the LSI53C895A does not interrupt if a master parity error occurs. This bit is cleared at power-up. FBL[2:0] FIFO Byte Control...
  • Page 170 Register: 0x22 Chip Test Five (CTEST5) Read/Write ADCK BBCK MASR DDIR BO[9:8] ADCK Clock Address Incrementor Setting this bit increments the address pointer contained in the DMA Next Address (DNAD) register. The DNAD register is incremented based on the DNAD contents and the current DBC value.
  • Page 171 transferred from the SCSI bus to the host bus. Deasserting the internal DMA write signal transfers data from the host bus to the SCSI bus. Burst Length Bit 2 This bit works with bits 6 and 7 (BL[1:0]) in the Mode (DMODE), 0x38 register to determine the burst length.
  • Page 172 Block Move and a value of 0x000000 is loaded into the DBC register, an illegal instruction interrupt occurs if the LSI53C895A is not in target mode, Command phase. The DBC register is also used to hold the least significant 24 bits of the first Dword of a SCRIPTS fetch, and to hold the offset value during table indirect I/O SCRIPTS.
  • Page 173 DCMD DMA Command [7:0] This 8-bit register determines the instruction for the LSI53C895A to execute. This register has a different format for each instruction. For a complete description Chapter 5, “SCSI SCRIPTS Instruction Set.” Registers: 0x28–0x2B DMA Next Address (DNAD)

  • Page 174: Second Dword

    the SCRIPT is written to this register, SCRIPTS are automatically fetched and executed until an interrupt condition occurs. In single step mode, there is a single step interrupt after each instruction is executed. The DMA SCRIPTS Pointer (DSP) register does not need to be written with the next address, but the Start DMA bit (bit 2, DMA Control (DCNTL)
  • Page 175 The LSI53C895A asserts the Bus Request (REQ/) output when the DMA FIFO can accommodate a transfer of at least one burst threshold of data. Bus Request...
  • Page 176 I/O space; and if cleared, then the source address is in memory space. This function is useful for register-to-memory operations using the Memory Move instruction when the LSI53C895A is I/O mapped. Bits 4 and 5 of the Chip Test Two (CTEST2) register are used to determine the configuration status of the LSI53C895A.
  • Page 177 I/O space; and if cleared, then the destination address is in memory space. This function is useful for memory-to-register operations using the Memory Move instruction when the LSI53C895A is I/O mapped. Bits 4 and 5 of the Chip Test Two (CTEST2) register are used to determine the configuration status of the LSI53C895A.
  • Page 178 automatically begin fetching and executing SCSI SCRIPTS when the DSP register is written. This bit normally is not used for SCSI SCRIPTS operations. Register: 0x39 DMA Interrupt Enable (DIEN) Read/Write MDPE ABRT Reserved MDPE Master Data Parity Error Bus Fault ABRT Aborted Single Step Interrupt...
  • Page 179 Read/Write CLSE PFEN IRQM IRQD CLSE Cache Line Size Enable Setting this bit enables the LSI53C895A to sense and react to cache line boundaries set up by the DMA Mode (DMODE) or PCI Cache Line Size register, whichever contains the smaller value. Clearing this bit disables the cache line size logic and the LSI53C895A monitors the cache line size using the DMODE register.
  • Page 180 8 Dwords of instructions and instruction operands in bursts of 4 or 8 Dwords. Prefetching instructions allows the LSI53C895A to make more efficient use of the system PCI bus, thus improving overall system performance. The unit will flush whenever the PFF bit is...
  • Page 181 DMA SCRIPTS Pointer (DSP) register when this bit is set. This bit is required if the LSI53C895A is in one of the following modes: • Manual start mode – Bit 0 in the DMA Mode...
  • Page 182 When the COM bit is set, the ID is stored only in the SSID register, protecting the SFBR from being overwritten if a selection/reselection occurs during a DMA register-to-register operation. Registers: 0x3C–0x3F Adder Sum Output (ADDER) Read Only ADDER ADDER Adder Sum Output [31:0] This register contains the output of the internal adder,...
  • Page 183 Function Complete Indicates full arbitration and selection sequence is completed. Selected Indicates the LSI53C895A is selected by a SCSI initiator device. Set the Enable Response to Selection bit in the SCSI Chip ID (SCID) register for this to occur. Reselected Indicates the LSI53C895A is reselected by a SCSI target device.
  • Page 184 SCSI Reset Condition Indicates assertion of the SRST/ signal by the LSI53C895A or any other SCSI device. This condition is edge-triggered, so multiple interrupts cannot occur because of a single SRST/ pulse. SCSI Parity Error Indicates detection by the LSI53C895A of a parity error while receiving or sending SCSI data.
  • Page 185 Reserved Selection or Reselection Time-out The SCSI device which the LSI53C895A is attempting to select or reselect does not respond within the programmed time-out period. See the description of the SCSI Timer Zero (STIME0) register bits [3:0] for more information on the time-out timer.
  • Page 186 This bit is set when an arbitration only or full arbitration sequence is completed. Selected This bit is set when the LSI53C895A is selected by another SCSI device. The Enable Response to Selection bit must be set in the SCSI Chip ID (SCID)
  • Page 187 FIFO. Unexpected Disconnect This bit is set when the LSI53C895A is operating in the initiator mode and the target device unexpectedly disconnects from the SCSI bus. This bit is only valid when the LSI53C895A operates in the initiator mode.
  • Page 188 SE, LVD or HVD modes. Reserved Selection or Reselection Time-out The SCSI device which the LSI53C895A is attempting to select or reselect does not respond within the programmed time-out period. See the description of the SCSI Timer Zero (STIME0) register, bits [3:0], for more information on the time-out timer.
  • Page 189 Handshake-to-Handshake Timer Expired This bit is set when the handshake-to-handshake timer expires. The time measured is the SCSI Request to Request (target) or Acknowledge-to-Acknowledge (initiator) period. See the description of the SCSI Timer Zero (STIME0) register, bits [7:4], for more information on the handshake-to-handshake timer.
  • Page 190 contains the appropriate check byte at the end of the block move. This byte must then be sent across the SCSI bus. Note: Writing any value to this register clears it to zero. The longitudinal parity checks are meant to provide an added measure of SCSI data integrity and are entirely optional.
  • Page 191 Wide Residue message is received. It may also be an overrun data byte. The power-up value of this register is indeterminate. Register: 0x46 Memory Access Control (MACNTL) Read/Write PSCPT SCPTS Chip Type [7:4] These bits identify the chip type for software purposes. Note: These bits no longer identify an 8XX device.
  • Page 192 6 of GPCNTL0 is cleared and the chip is not in progress of performing an EEPROM autodownload regardless of the state of bit 0 (GPIO0). This provides a hardware solution to driving a SCSI activity LED in many implementations of LSI Logic SCSI chips. GPIO GPIO Enable...
  • Page 193 GPIO GPIO Enable [1:0] These bits power-up set, causing the GPIO1 and GPIO0 pins to become inputs. Clearing these bits causes GPIO[1:0] to become outputs. Register: 0x48 SCSI Timer Zero (STIME0) Read/Write HTH[3:0] SEL[3:0] HTH[3:0] Handshake-to-Handshake Timer Period [7:4] These bits select the handshake-to-handshake time-out period, the maximum time between SCSI handshakes (SREQ/ to SREQ/ in target mode, or SACK/ to SACK/ in initiator mode).
  • Page 194 HTH [3:0] Minimum Time-out Minimum Time-out SEL [3:0] (80 MHz Clock) With (80 MHz Clock) With GEN [3:0] Scale Factor Bit Cleared Scale Factor Bit Set 0000 Disabled Disabled 100 µs 0001 1.6 ms 200 µs 0010 3.2 ms 400 µs 0011 6.4 ms 800 µs...
  • Page 195 Register: 0x49 SCSI Timer One (STIME1) Read/Write HTHBA GENSF HTHSF GEN[3:0] Reserved HTHBA Handshake-to-Handshake Timer Bus Activity Enable Setting this bit causes this timer to begin testing for SCSI REQ/, ACK/ activity as soon as SBSY/ is asserted, regardless of the agents participating in the transfer. GENSF General Purpose Timer Scale Factor Setting this bit causes this timer to shift by a factor of 16.
  • Page 196 Register: 0x4A Response ID Zero (RESPID0) Read/Write RESPID0 and Response ID One (RESPID1) contain the selection or reselection IDs. In other words, these two 8-bit registers contain the ID that the chip responds to on the SCSI bus. Each bit represents one possible ID with the most significant bit of RESPID1 representing ID 15 and the least significant bit of RESPID0 representing ID 0.
  • Page 197 LSI53C895A can respond to. During a SCSI selection phase, when a valid ID is put on the bus, and the LSI53C895A responds to that ID, the ID that the chip was selected as will be written into the SSAID[3:0] bits.
  • Page 198 It is used in low level synchronous SCSI operations. When this bit is set, the LSI53C895A, as a target, is waiting for the initiator to acknowledge the data transfers. If the LSI53C895A is an initiator, then the target has sent the offset number of requests.
  • Page 199 Setting this bit allows assertion of all SCSI control and data lines through the SCSI Output Control Latch (SOCL) SCSI Output Data Latch (SODL) registers regardless of whether the LSI53C895A is configured as a target or initiator. SCSI Registers 4-91...
  • Page 200 The bit automatically clears itself after resetting the synchronous offset. HVD or SE/LVD Setting this bit allows the LSI53C895A to interface to external HVD transceivers. Clearing this bit enables SE or LVD operation. Set this bit in the initialization routine if the differential pair interface is used.
  • Page 201 SCSI Low level Mode Setting this bit places the LSI53C895A in the low level mode. In this mode, no DMA operations occur, and no SCRIPTS execute. Arbitration and selection may be...
  • Page 202 Disable Single Initiator Response If this bit is set, the LSI53C895A ignores all bus-initiated selection attempts that employ the single initiator option from SCSI-1. In order to select the LSI53C895A while this bit is set, the LSI53C895A’s SCSI ID and the initiator’s SCSI ID must both be asserted.
  • Page 203 Setting this bit starts all three timers and if the respective bits in the SCSI Interrupt Enable One (SIEN1) register are asserted, the LSI53C895A generates interrupts at time-out. This bit is intended for internal manufacturing diagnosis and should not be used. Clear SCSI FIFO Setting this bit causes the “full flags”...
  • Page 204 SCSI Output Data Latch (SODL) register and then read back into the LSI53C895A by reading this register to allow loopback testing. When receiving SCSI data, the data flows into this register and out to the host FIFO. This register differs...
  • Page 205 Frequency Lock This bit is used when enabling the SCSI clock quadrupler, which allows the LSI53C895A to transfer data at Ultra2 SCSI rates. Poll this bit for a 1 to determine that the clock quadrupler has locked to 160 MHz. For more information...
  • Page 206 WSR bit is cleared and Phase Mismatch Jump Address 2 (PMJAD2) when the WSR bit is set. When this bit is set the LSI53C895A will use jump address one (PMJAD1) on data out (data out, command, message out) transfers and jump address two (PMJAD2) on data in (data in, status, message in) transfers.
  • Page 207 ENNDJ Enable Jump On Nondata Phase Mismatches This bit controls whether or not a jump is taken during a nondata phase mismatch (i.e. message in, message out, status, or command). When this bit is clear, jumps will only be taken on Data-In or Data-Out phases and a phase mismatch interrupt will be generated for all other phases.
  • Page 208 LSI53C895A signals in the “AND-tree” test mode. In order to read data out of the LSI53C895A, this bit must be cleared. This bit is intended for board-level testing only. Do not set this bit during normal system operation.

  • Page 209: First Dword

    Index Mode 1 (64TIMOD set) table entry format: [31:24] [23:0] Src/Dest Addr [39:32] Byte Count Source/Destination Address [31:0] EN64TIBMV Enable 64-Bit Table Indirect BMOV Setting this bit enables 64-bit addressing for Table Indirect BMOVs using the upper byte (bit [24:31]) of the first Dword of the table entry.
  • Page 210 Register: 0x5A General Purpose Pin Control One (GPCNTL1) Read/Write GPIOEN[8:5] This register is used to determine if the signals controlled by the General Purpose One register are inputs or outputs. Bits [3:0] in GPCNTL1 correspond to bits [3:0] in General Purpose Pin Control One (GPCNTL1) register.
  • Page 211 Registers: 0x5C–0x5F Scratch Register B (SCRATCHB) Read/Write SCRATCHB SCRATCHB Scratch Register B [31:0] This is a general purpose user definable scratch pad register. Apart from CPU access, only register Read/Write and Memory Moves directed at the SCRATCH register will alter its contents. The power-up values are indeterminate.
  • Page 212 A special mode of this register can be enabled by setting the PCI Configuration Enable bit in the Chip Test Two (CTEST2) register. Because the LSI53C895A supports only a 32-bit memory mapped PCI base address, the MMRS register is always read as 0x00000000 when in the special mode.
  • Page 213 A special mode of this register can be enabled by setting the PCI Configuration Into Enable bit in the Chip Test Two (CTEST2) register. Because the LSI53C895A supports only a 32-bit SCRIPTS RAM PCI base address, the MMWS register is always read as 0x00000000 when in the special mode.
  • Page 214 register return the PCI Revision ID (Rev ID) register value and bits [15:0] return the PCI Device ID register value when read. Writes to the SFS register are unaffected. Clearing the PCI Configuration Into Enable bit causes the SFS register to return to normal operation.
  • Page 215 Registers: 0xB4–0xB7 Dynamic Block Move Selector (DBMS) Read/Write DBMS DBMS Dynamic Block Move Selector [31:0] Supplies the upper Dword of a 64-bit address during block move operations, reads or writes. This register is used only during 64-bit direct BMOV instructions and will be reloaded with the upper 32-bit data address upon execution of a 64-bit direct BMOVs.
  • Page 216 4.4 Phase Mismatch Jump Registers Eight 32-bit registers contain the byte count and addressing information required to update the direct, indirect, or table indirect BMOV instructions with new byte counts and addresses. The eight register descriptions follow. All registers can be read/written using the Load and Store SCRIPTS instructions, Memory-to-Memory Moves, read/write SCRIPTS instructions, or the CPU with SCRIPTS not running.
  • Page 217 Registers: 0xC4–0xC7 Phase Mismatch Jump Address 2 (PMJAD2) Read/Write PMJAD2 PMJAD2 Phase Mismatch Jump Address 2 [31:0] This register contains the 32-bit address that will be jumped to upon a phase mismatch. Depending upon the state of the PMJCTL bit in register Chip Control 0 (CCNTL0) this address will either be used during an...
  • Page 218 memory with the exception of a possible byte in the SWIDE register. That byte must be flushed to memory manually in SCRIPTS. In the case of a SCSI data send, this byte count will reflect all data sent out onto the SCSI bus. Any data left in the part from the phase mismatch will be ignored and automatically cleared from the FIFOs.
  • Page 219 Registers: 0xD0–0xD3 Entry Storage Address (ESA) Read/Write Entry Storage Address [31:0] This register's value depends on the type of BMOV being executed. The three types of BMOVs are listed below. Direct BMOV: In the case of a direct BMOV, this register will contain the address the BMOV was fetched from when the phase mismatch occurred.
  • Page 220 Registers: 0xD8–0xDA SCSI Byte Count (SBC) Read only SCSI Byte Count [23:0] This register contains the count of the number of bytes transferred to or from the SCSI bus during any given BMOV. This value is used in calculating the information placed into the Remaining Byte Count (RBC) Updated Address (UA)
  • Page 221 the SCSI bus during data phases, i.e. it will not count bytes sent in command, status, message in or message out phases. It will count bytes as long as the phase mismatch enable (ENPMJ) bit in the Chip Control 0 (CCNTL0) register is set.
  • Page 222 4-114 Registers...
  • Page 223 Section 5.7, “Memory Move Instructions” • Section 5.8, “Load and Store Instructions” After power-up and initialization, the LSI53C895A can be operated in the low level register interface mode or in the high level SCSI SCRIPTS mode. 5.1 Low Level Register Interface Mode With the low level register interface mode, the user has access to the DMA control logic and the SCSI bus control logic.
  • Page 224 5.2 High Level SCSI SCRIPTS Mode To operate in the SCSI SCRIPTS mode, the LSI53C895A requires only a SCRIPTS start address. The start address must be at a Dword (four byte) boundary.
  • Page 225 • Loading the DMA SCRIPTS Pointer (DSP) register causes the LSI53C895A to fetch its first instruction at the address just loaded. This is from main memory or the internal RAM, depending on the address. High Level SCSI SCRIPTS Mode...
  • Page 226 LSI53C895A requests use of the PCI bus again to transfer the data. • When the LSI53C895A is granted the PCI bus, it executes (as a bus master) a burst transfer (programmable size) of data, decrement the internally stored remaining byte count, increment the address pointer, and then release the PCI bus.
  • Page 227 × Move from data_buf when DATA_OUT × Move from stat_in_buf, when STATUS × Move SCNTL2 & 7F to SCNTL2 × Clear ACK Fetch × Wail disconnect alt2 SCRIPTS LSI53C895A SCSI Bus × Int 10 For details, Table see block diagram in...

  • Page 228: Second Dword

    5.3.1 First Dword 31 30 29 28 24 23 16 15 DMA Command (DCMD) Register DMA Byte Counter (DBC) Register IT[1:0] IA TIA OPC SCSIP[2:0] Transfer Counter [23:0] x x x x x x x x x x x x x x x x x x x x x x x x IT[1:0] Instruction Type - Block Move [31:30]...
  • Page 229 This indirect feature allows a table of data buffer addresses to be specified. Using the LSI Logic SCSI SCRIPTS assembler, the table offset is placed in the script at compile time. Then at the actual data transfer time, the offsets are added to the base address of the data address table by the external processor.
  • Page 230 For a MOVE instruction, the 24-bit byte count is fetched from system memory. Then the 32-bit physical address is brought into the LSI53C895A. Execution of the move begins at this point. SCRIPTS can directly execute operating system I/O data structures, saving time at the beginning of an I/O operation.
  • Page 231 These instructions perform the following steps: 1. The LSI53C895A verifies that it is connected to the SCSI bus as a Target before executing this instruction. 2. The LSI53C895A asserts the SCSI phase signals (SMSG/, SC_D/, and SI_O/) as defined by the Phase Field bits in the instruction.
  • Page 232 CHMOV MOVE These instructions perform the following steps: 1. The LSI53C895A verifies that it is connected to the SCSI bus as an Initiator before executing this instruction. 2. The LSI53C895A waits for an unserviced phase to occur. An unserviced phase is any phase (with SREQ/ asserted) for which the LSI53C895A has not yet transferred data by responding with a SACK/.

  • Page 233: Scsi Information Transfer Phase

    Set ATN instruction), the LSI53C895A deasserts SATN/ during the final SREQ/SACK/ handshake. 7. When the LSI53C895A is performing a block move for Message-In phase, it does not deassert the SACK/ signal for the last SREQ/SACK/ handshake. Clear the SACK/ signal using the Clear SACK I/O instruction.
  • Page 234 TC[23:0] Transfer Counter [23:0] This 24-bit field specifies the number of data bytes to be moved between the LSI53C895A and system memory. The field is stored in the DMA Byte Counter (DBC) register. When the LSI53C895A transfers data to/from memory, the DBC register is decremented by the number of bytes transferred.

  • Page 235: Read/Write Instructions

    5.4 I/O Instruction I/O Instructions perform the following SCSI operations in Target and Initiator mode. These I/O operations are chosen with the opcode bits in DMA Command (DCMD) register. OPC2 OPC1 OPC0 Target Mode Initiator Mode Reselect Select Disconnect Wait Disconnect Wait Select Wait Reselect Clear...
  • Page 236 32-bit jump address field stored in the DMA Next Address (DNAD) register. Manually set the LSI53C895A to Initiator mode if it is reselected, or to Target mode if it is selected. Disconnect Instruction The LSI53C895A disconnects from the SCSI bus by deasserting all SCSI signal outputs.
  • Page 237 32-bit jump address field stored in the DMA Next Address (DNAD) register. Manually set the LSI53C895A to Initiator mode when it is reselected. If the CPU sets the SIGP bit in the Interrupt Status Zero...
  • Page 238 DMA Next Address (DNAD) register. Manually set the LSI53C895A to Initiator mode if it is reselected, or to Target mode if it is selected. If the Select with SATN/ field is set, the SATN/ signal is asserted during the selection phase.
  • Page 239 Wait Reselect Instruction If the LSI53C895A is selected before being reselected, it fetches the next instruction from the address pointed to by the 32-bit jump address field stored in the DMA Next Address (DNAD) register. Manually set the LSI53C895A to Target mode when it is selected.
  • Page 240 Data Structure Address (DSA) register, and used as an offset relative to the value in the Data Structure Address (DSA) register. The SCSI Control Three (SCNTL3) value, SCSI ID, synchronous offset and synchronous period are loaded from this address. Prior to the start of an I/O, load Data Structure Address (DSA) with the base address of the I/O data structure.
  • Page 241 Command Table Offset Alternate Jump Offset Select with ATN/ This bit specifies whether SATN/ is asserted during the selection phase when the LSI53C895A is executing a Select instruction. When operating in Initiator mode, set I/O Instruction 5-19...
  • Page 242 This bit is used in conjunction with a Set or Clear instruction to set or clear Target mode. Setting this bit with a Set instruction configures the LSI53C895A as a Target device (this sets bit 0 of the SCSI Control Zero (SCNTL0) register).

  • Page 243: Second Dword

    Since SACK/ and SATN/ are Initiator signals, they are not asserted on the SCSI bus unless the LSI53C895A is operating as an Initiator or the SCSI Loopback Enable bit is set in the SCSI Test Two (STEST2) register. The Set/Clear SCSI ACK/, ATN/ instruction is used after...

  • Page 244: Read/Write Instructions

    5.5 Read/Write Instructions The Read/Write instruction supports addition, subtraction, and comparison of two separate values within the chip. It performs the desired operation on the specified register and the SCSI First Byte Received (SFBR) register, then stores the result back to the specified register or the SFBR.

  • Page 245: Read-Modify-Write Cycles

    [22:16] It is possible to change register values from SCRIPTS in read-modify-write cycles or move to/from SFBR cycles. A[6:0] selects an 8-bit source/destination register within the LSI53C895A. ImmD Immediate Data [15:8] This 8-bit value is used as a second operand in logical and arithmetic functions.

  • Page 246: Read/Write Instructions

    5.5.4 Move To/From SFBR Cycles All operations are read-modify-writes. However, two registers are involved, one of which is always the SFBR. Table 5.3 shows the possible read-modify-write operations. The possible functions of this instruction are: • Write one byte (value contained within the SCRIPTS instruction) into any chip register.
  • Page 247 Table 5.3 Read/Write Instructions (Cont.) OpCode 111 OpCode 110 OpCode 101 Operator Read-Modify-Write Move to SFBR Move from SFBR AND data with register and AND data with register and AND data with SFBR and place the result in the same place the result in the SCSI place the result in the...

  • Page 248: Transfer Control Instructions

    5.6 Transfer Control Instructions This section describes the Transfer Control Instructions. The configuration of the OpCode bits define which Transfer Control Instruction to perform. 5.6.1 First Dword 31 30 29 27 26 24 23 22 21 20 19 18 17 16 15 DMA Command (DCMD) DMA Byte Counter (DBC)
  • Page 249 Jump Instruction The LSI53C895A can do a true/false comparison of the ALU carry bit, or compare the phase and/or data as defined by the Phase Compare, Data Compare and True/False bit fields. If the comparisons are true, then it loads the...
  • Page 250 Temporary (TEMP) register is returned to the DSP register. The LSI53C895A does not check to see whether the Call instruction has already been executed. It does not generate an interrupt if a Return instruction is executed without previously executing a Call instruction.

  • Page 251: Scsi Phase Comparisons

    LSI53C895A is operating in Initiator mode. Clear these bits when the LSI53C895A is operating in Target mode. Table 5.5 SCSI Phase Comparisons SCSI Phase Data-Out Data-In Command Status Reserved Reserved Message-Out Message-In Relative Addressing Mode When this bit is set, the 24-bit signed value in the...
  • Page 252 The SCRIPTS program counter is a 32-bit value pointing to the SCRIPTS currently under execution by the LSI53C895A. The next address is formed by adding the 32-bit program counter to the 24-bit signed value of the last 24 bits of the Jump or Call instruction. Because it is signed (2’s complement), the jump can be forward or...
  • Page 253 SCSI SATN/ signal. Wait For Valid Phase If the Wait for Valid Phase bit is set, the LSI53C895A waits for a previously unserviced phase before comparing the SCSI phase and data.

  • Page 254: Second Dword

    The Memory Move instruction is used to copy the specified number of bytes from the source address to the destination address. Allowing the LSI53C895A to perform memory moves frees the system processor for other tasks and moves data at higher speeds than available from current DMA controllers.

  • Page 255: First Dword

    These bits are reserved and must be zero. If any of these bits are set, an illegal instruction interrupt occurs. No Flush When this bit is set, the LSI53C895A performs a Memory Move without flushing the prefetch unit. When this bit is cleared, the Memory Move instruction automatically flushes the prefetch unit.

  • Page 256: Read/Write System Memory From Scripts

    5.7.2 Read/Write System Memory from SCRIPTS By using the Memory Move instruction, single or multiple register values are transferred to or from system memory. Because the LSI53C895A responds to addresses as defined in the Base Address Register Zero (I/O) Base Address Register One (MEMORY) registers, it can be accessed during a Memory Move operation if the source or destination address decodes to within the chip’s register space.

  • Page 257: Third Dword

    5.7.4 Third Dword 24 23 16 15 Temporary (TEMP) Register TEMP Register [31:0] These bits contain the destination address for the Memory Move. 5.8 Load and Store Instructions The Load and Store instructions provide a more efficient way to move data from/to memory to/from an internal register in the chip without using the normal memory move instruction.
  • Page 258 Reserved [27:26] No Flush (Store instruction only) When this bit is set, the LSI53C895A performs a Store without flushing the prefetch unit. When this bit is cleared, the Store instruction automatically flushes the prefetch unit. Use No Flush if the source and destination are not within four instructions of the current Store instruction.
  • Page 259 Store. Reserved RA[6:0] Register Address [22:16] A[6:0] selects the register to Load and Store to/from within the LSI53C895A. Reserved [15:3] Byte Count [2:0] This value is the number of bytes to Load and Store. 5.8.2 Second Dword...
  • Page 260 5-38 SCSI SCRIPTS Instruction Set...

  • Page 261: Electrical Specifications

    Section 6.4, “PCI and External Memory Interface Timing Diagrams” • Section 6.5, “SCSI Timing Diagrams” • Section 6.6, “Package Diagrams” 6.1 DC Characteristics This section of the manual describes the LSI53C895A DC characteristics. Tables through 6.13 give current and voltage specifications. Figures are driver schematics.

  • Page 262: Absolute Maximum Stress Ratings

    Table 6.1 Absolute Maximum Stress Ratings Symbol Parameter Unit Test Conditions −55 °C Storage temperature – −0.5 Supply voltage – −0.3 V +0.3 Input voltage −0.3 Input voltage (5 V tolerant pins) 5.25 – IN5V ±150 Latch-up current – – Electrostatic discharge –...

  • Page 263: Lvd Driver

    Table 6.3 LVD Driver SCSI Signals—SD[15:0]+, SDP[1:0]/, SREQ/, SREQ2/, SACK/, SACK2/, SMSG/, SIO/, SCD/, SATN/, SBSY/, SSEL/, SRST/ Symbol Parameter Unit Test Conditions Source (+) current Asserted state − −7 −13 Sink (−) current Asserted state −6.5 Source (+) current Negated state −...

  • Page 264: Lvd Receiver

    Figure 6.2 LVD Receiver − − − − Table 6.5 DIFFSENS SCSI Signal Symbol Parameter Unit Test Conditions HVD sense voltage Note 1 LVD sense voltage Note 1 −0.3 SE sense voltage Note 1 −10 µA Input leakage = 0 V, 5.25 V 1.

  • Page 265: Bidirectional Signals—Mad[7:0], Mas/[1:0], Mce Moe/, Mwe/

    Table 6.7 Bidirectional Signals—MAD[7:0], MAS/[1:0], MCE/, MOE/, MWE/ Symbol Parameter Unit Test Conditions Input high voltage 5.25 – −0.3 Input low voltage – −4 mA dynamic Output high voltage Output low voltage 4 mA dynamic −10 µA 3-state leakage = 0 V, 5.25 V µA Pull-down current –...

  • Page 266: Bidirectional Signals—Ad[31:0], C_Be[3:0]/, Frame Irdy/, Trdy/, Devsel/, Stop/, Perr/, Par

    Table 6.9 Bidirectional Signals—AD[31:0], C_BE[3:0]/, FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR Symbol Parameter Unit Test Conditions Input high voltage 0.5 V 5.25 – −0.3 Input low voltage 0.3 V – −500 µA Output high voltage 0.9 V – 1500 µA Output low voltage –...

  • Page 267: Output Signal—Tdo

    Table 6.11 Output Signal—TDO Symbol Parameter Unit Test Conditions −4 mA dynamic Output high voltage Output low voltage 4 mA dynamic −10 µA 3-state leakage = 0 V, 5.25 V Table 6.12 Output Signals—ALT_IRQ/, IRQ/, MAC/_TESTOUT, REQ/ Symbol Parameter Unit Test Conditions −500 µA Output high voltage...

  • Page 268: Tolerant Technology Electrical Characteristics

    6.2 TolerANT Technology Electrical Characteristics The LSI53C895A features TolerANT technology, which includes active negation on the SCSI drivers and input signal filtering on the SCSI receivers. Active negation actively drives the SCSI Request, Acknowledge, Data, and Parity signals HIGH rather than allowing them to be passively pulled up by terminators.

  • Page 269: Rise And Fall Time Test Condition

    Table 6.14 TolerANT Technology Electrical Characteristics for SE SCSI Signals (Cont.) Symbol Parameter Unit Test Conditions Fall time, 90% to 10% 18.5 Figure 6.3 Slew rate, LOW to HIGH 0.15 0.50 V/ns Figure 6.3 Slew rate, HIGH to LOW 0.15 0.50 V/ns Figure 6.3...

  • Page 270: Hysteresis Of Scsi Receivers

    Figure 6.5 Hysteresis of SCSI Receivers Input Voltage (Volts) Figure 6.6 Input Current as a Function of Input Voltage 14.4 V 8.2 V − 0.7 V HIGH-Z OUTPUT − 20 ACTIVE − 40 − 4 Input Voltage (Volts) 6-10 Electrical Specifications...

  • Page 271: Output Current As A Function Of Output Voltage

    Figure 6.7 Output Current as a Function of Output Voltage − 200 − 400 − 600 − 800 Output Voltage (Volts) Output Voltage (Volts) TolerANT Technology Electrical Characteristics 6-11...

  • Page 272: Ac Characteristics

    6.3 AC Characteristics The AC characteristics described in this section apply over the entire range of operating conditions (refer to the DC Characteristics section). Chip timings are based on simulation at worst case voltage, temperature, and processing. Timing was developed with a load capacitance of 50 pF. Table 6.15 Figure 6.8 provide External Clock timing data.

  • Page 273: Reset Input

    Table 6.16 Figure 6.9 provide Reset Input timing data. Table 6.16 Reset Input Symbol Parameter Unit Reset pulse width – Reset deasserted setup to CLK HIGH – MAD setup time to CLK HIGH – (for configuring the MAD bus only) MAD hold time from CLK HIGH –...

  • Page 274: Pci And External Memory Interface Timing Diagrams

    Figures 6.11 through 6.34 represent signal activity when the LSI53C895A accesses the PCI bus. This section includes timing diagrams for access to three groups of memory configurations. The first group applies to Target Timing. The second group applies to Initiator Timing.

  • Page 275: Target Timing

    – 32-Bit Operating Register/SCRIPTS RAM Write – 64-Bit Address Operating Register/SCRIPTS RAM Write • Initiator Timing – Nonburst Opcode Fetch, 32-Bit Address and Data – Burst Opcode Fetch, 32-Bit Address and Data – Back to Back Read, 32-Bit Address and Data –...

  • Page 276: Pci Configuration Register Read

    Addr (Driven by Master-Addr; Data Out LSI53C895A-Data) C_BE/ Byte Enable (Driven by Master (Driven by Master-Addr; LSI53C895A-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C895A) STOP/ (Driven by LSI53C895A) DEVSEL/ (Driven by LSI53C895A) IDSEL (Driven by Master) 6-16 Electrical Specifications...

  • Page 277: Pci Configuration Register Write

    (Driven by Master) C_BE/ Byte Enable (Driven by Master) (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C895A) STOP/ (Driven by LSI53C895A) DEVSEL/ (Driven by LSI53C895A) IDSEL (Driven by Master) PCI and External Memory Interface Timing Diagrams 6-17...

  • Page 278: Bit Operating Register/Scripts Ram Read

    (Driven by System) FRAME/ (Driven by Master) Data Addr (Driven by Master-Addr; LSI53C895A-Data) C_BE/ Byte Enable (Driven by Master) (Driven by Master-Addr; LSI53C895A-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C895A) STOP/ (Driven by LSI53C895A) DEVSEL/ (Driven by LSI53C895A) 6-18 Electrical Specifications...

  • Page 279: Bit Address Operating Register/Scripts Ram Read

    (Driven by Master-Addr; LSI53C895A-Data) C_BE[3:0] Dual Byte Enable (Driven by Master) Addr (Driven by Master-Addr; LSI53C895A-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C895A) STOP/ (Driven by LSI53C895A) DEVSEL/ (Driven by LSI53C895A) PCI and External Memory Interface Timing Diagrams 6-19...

  • Page 280: Bit Operating Register/Scripts Ram Write

    Figure 6.15 32-Bit Operating Register/SCRIPTS RAM Write (Driven by System) FRAME/ (Driven by Master) Addr (Driven by Master) C_BE/ (Driven by Master) (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C895A) STOP/ (Driven by LSI53C895A) DEVSEL/ (Driven by LSI53C895A) 6-20 Electrical Specifications...

  • Page 281: Bit Address Operating Register/Scripts Ram Write

    Data In (Driven by Master) C_BE/ Dual Byte Enable (Driven by Master) Addr (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C895A) STOP/ (Driven by LSI53C895A) DEVSEL/ (Driven by LSI53C895A) PCI and External Memory Interface Timing Diagrams 6-21...

  • Page 282: Initiator Timing

    6.4.2 Initiator Timing Tables 6.24 through 6.31 and Figures 6.17 6.24 describe Initiator timing. Table 6.24 Nonburst Opcode Fetch, 32-Bit Address and Data Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid Side signal input setup time –...

  • Page 283: Nonburst Opcode Fetch, 32-Bit Address And Data

    Figure 6.17 Nonburst Opcode Fetch, 32-Bit Address and Data (Driven by System) GPIO0_FETCH/ (Driven by LSI53C895A) GPIO1_MASTER/ (Driven by LSI53C895A) REQ/ (Driven by LSI53C895A) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C895A) Data Addr Addr Data (Driven by LSI53C895A- Addr; Target-Data)

  • Page 284: Burst Opcode Fetch, 32-Bit Address And Data

    Table 6.25 Burst Opcode Fetch, 32-Bit Address and Data Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid Side signal input setup time – Side signal input hold time –...

  • Page 285: Burst Opcode Fetch, 32-Bit Address And Data

    Figure 6.18 Burst Opcode Fetch, 32-Bit Address and Data (Driven by System) GPIO0_FETCH/ (Driven by LSI53C895A) GPIO1_MASTER/ (Driven by LSI53C895A) REQ/ (Driven by LSI53C895A) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C895A) Data Data Addr (Driven by LSI53C895A- Addr; Target-Data)

  • Page 286: Back To Back Read, 32-Bit Address And Data

    Table 6.26 Back to Back Read, 32-Bit Address and Data Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid Side signal input setup time – Side signal input hold time –...

  • Page 287: Back To Back Read, 32-Bit Address And Data

    Figure 6.19 Back to Back Read, 32-Bit Address and Data (Driven by System) GPIO0_FETCH/ (Driven by LSI53C895A GPIO1_MASTER/ (Driven by LSI53C895A) REQ/ (Driven by LSI53C895A) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C895A) Data In Data In Addr Addr (Driven by LSI53C895A- Addr;...

  • Page 288: Back To Back Write, 32-Bit Address And Data

    Table 6.27 Back to Back Write, 32-Bit Address and Data Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid Side signal input setup time – Side signal input hold time –...

  • Page 289: Back To Back Write, 32-Bit Address And Data

    Figure 6.20 Back to Back Write, 32-Bit Address and Data (Driven by System) GPIO0_FETCH/ (Driven by LSI53C895A) GPIO1_MASTER/ (Driven by LSI53C895A) REQ/ (Driven by LSI53C895A) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C895A) AD[31:0] Data Data Addr Addr (Driven by LSI53C895A- Addr;...

  • Page 290: Burst Read, 32-Bit Address And Data

    Table 6.28 Burst Read, 32-Bit Address and Data Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid 6-30 Electrical Specifications...

  • Page 291: Burst Read, 32-Bit Address And Data

    Figure 6.21 Burst Read, 32-Bit Address and Data GPIO0_FETCH/ (Driven by LSI53C895A) GPIO1_MASTER/ (Driven by LSI53C895A) REQ/ (Driven by LSI53C895A) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C895A) Data In Addr (Driven by LSI53C895A- Addr; Target-Data) C_BE/ (Driven by LSI53C895A) (Driven by LSI53C895A- Addr;...

  • Page 292: Burst Read, 64-Bit Address And Data

    Table 6.29 Burst Read, 64-Bit Address and Data Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid CLK HIGH to GPIO1_MASTER/ HIGH – 6-32 Electrical Specifications...

  • Page 293: Burst Read, 64-Bit Address And Data

    Figure 6.22 Burst Read, 64-Bit Address and Data (Driven by System) GPIO0_FETCH/ (Driven by LSI53C895A) GPIO1_MASTER/ (Driven by LSI53C895A) REQ/ (Driven by LSI53C895A) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C895A) Addr Data Data (Driven by LSI53C895A) C_BE/ (Driven by LSI53C895A)

  • Page 294: Burst Write, 32-Bit Address And Data

    Table 6.30 Burst Write, 32-Bit Address and Data Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid CLK HIGH to GPIO1_MASTER/ HIGH – 6-34 Electrical Specifications...

  • Page 295: Burst Write, 32-Bit Address And Data

    Figure 6.23 Burst Write, 32-Bit Address and Data (Driven by System) GPIO0_FETCH/ (Driven by LSI53C895A) GPIO1_MASTER/ (Driven by LSI53C895A) REQ/ (Driven by LSI53C895A) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C895A) Addr Data Data (Driven by LSI53C895A) C_BE/ (Driven by LSI53C895A)

  • Page 296: Burst Write, 64-Bit Address And 32-Bit Data

    Table 6.31 Burst Write, 64-Bit Address and 32-Bit Data Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid CLK HIGH to GPIO1_MASTER/ HIGH – 6-36 Electrical Specifications...

  • Page 297: Burst Write, 64-Bit Address And 32-Bit Data

    Figure 6.24 Burst Write, 64-Bit Address and 32-Bit Data (Driven by System) GPIO0_FETCH/ (Driven by LSI53C895A) GPIO1_MASTER/ (Driven by LSI53C895A) REQ/ (Driven by LSI53C895A) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C895A) AD[31:0] Addr Data Data Addr (Driven by LSI53C895A)
  • Page 298 This page intentionally left blank. 6-38 Electrical Specifications...

  • Page 299: External Memory Timing

    6.4.3 External Memory Timing Tables 6.32 through 6.39 and Figures 6.25 through 6.34 describe External Memory timing. Table 6.32 External Memory Read Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid –...

  • Page 300: External Memory Read

    (Driven by Master) TRDY/ (Driven by LSI53C895A) STOP/ (Driven by LSI53C895A) DEVSEL/ (Driven by LSI53C895A) Upper Middle Lower (Addr driven by LSI53C895A; Address Address Address Data driven by Memory) MAS1/ (Driven by LSI53C895A) MAS0/ (Driven by LSI53C895A) MCE/ (Driven by LSI53C895A)
  • Page 301 IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C895A) STOP/ (Driven by LSI53C895A) DEVSEL/ (Driven by LSI53C895A) Data Lower (Addr driven by LSI53C895A; Address Data driven by Memory) MAS1/ (Driven by LSI53C895A) MAS0/ (Driven by LSI53C895A) MCE/ (Driven by LSI53C895A) MOE/...
  • Page 302 This page intentionally left blank. 6-42 Electrical Specifications...

  • Page 303: External Memory Write

    Table 6.33 External Memory Write Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid – Address setup to MAS/ HIGH – Address hold from MAS/ HIGH – MAS/ pulse width –...

  • Page 304: External Memory Write

    Data In (Driven by Master) C_BE[3:0]/ Byte Enable (Driven by Master) (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C895A) STOP/ (Driven by LSI53C895A) DEVSEL/ (Driven by LSI53C895A) High Order Middle Order Low Order (Driven by LSI53C895A) Address...
  • Page 305 (Driven by Master) AD[31:0] (Driven by Master) C_BE[3:0]/ Byte Enable (Driven by Master) (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C895A) STOP/ (Driven by LSI53C895A) DEVSEL/ (Driven by LSI53C895A) Data Out (Driven by LSI53C895A) MAS1/ (Driven by LSI53C895A) MAS0/...

  • Page 306: Normal/Fast Memory ( ≥ 128 Kbytes) Single Byte Access Read Cycle

    Address out from MOE/, MCE/ HIGH – Data setup to CLK HIGH – Figure 6.27 Normal/Fast Memory ( ≥= 128 Kbytes) Single Byte Access Read Cycle Higher (Addr driven by LSI53C895A; Address Data driven by memory) MAS1/ (Driven by LSI53C895A) MAS0/...

  • Page 307: Normal/Fast Memory ( ≥ 128 Kbytes) Single Byte Access Write Cycle

    MCE/ LOW to MWE/ LOW – MWE/ HIGH to MCE/ HIGH – Figure 6.28 Normal/Fast Memory ( ≥= 128 Kbytes) Single Byte Access Write Cycle Higher Valid Write Data (Driven by LSI53C895A) Address MAS1/ (Driven by LSI53C895A) MAS0/ (Driven by LSI53C895A) MCE/...

  • Page 308: Normal/Fast Memory ( ≥ 128 Kbytes) Multiple Byte Access Read Cycle

    (Driven by Master) TRDY/ (Driven by LSI53C895A) STOP/ (Driven by LSI53C895A) DEVSEL/ (Driven by LSI53C895A) Upper Middle Lower (Addr Driven by LSI53C895A; Address Address Address Data driven by Memory) MAS1/ (Driven by LSI53C895A) MAS0/ (Driven by LSI53C895A) MCE/ (Driven by LSI53C895A)
  • Page 309 (Driven by Master) TRDY/ (Driven by LSI53C895A) STOP/ (Driven by LSI53C895A) DEVSEL/ (Driven by LSI53C895A) Data In Data In Lower (Addr Driven by LSI53C895A Address Data driven by Memory) MAS1/ (Driven by LSI53C895A) MAS0/ (Driven by LSI53C895A) MCE/ (Driven by LSI53C895A) MOE/...

  • Page 310: Normal/Fast Memory ( ≥ 128 Kbytes) Multiple Byte Access Write Cycle

    Addr AD[31:0] Data (Driven by Master) C_BE[3:0]/ Byte (Driven by Master) Enable (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C895A) STOP/ (Driven by LSI53C895A) DEVSEL/ (Driven by LSI53C895A) Middle Order High Order Order Data Out Address Address...
  • Page 311 AD[31:0] Data In (Driven by Master) C_BE[3:0]/ Byte Enable (Driven by Master) (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C895A) STOP/ (Driven by LSI53C895A) DEVSEL/ (Driven by LSI53C895A) Low Order Address Data Out (Driven by LSI53C895A) MAS1/...

  • Page 312: Slow Memory ( ≤ 128 Kbytes) Read Cycle

    – Data setup to CLK HIGH – Figure 6.31 Slow Memory ( ≤= 128 Kbytes) Read Cycle Valid Read Data Higher Middle Lower (Address driven by LSI53C895A; Address Address Address Data driven by Memory) MAS1/ (Driven by LSI53C895A) MAS0/ (Driven by LSI53C895A)

  • Page 313: Slow Memory ( ≤ 128 Kbytes) Write Cycle

    MCE/ LOW to MWE/ LOW – MWE/ HIGH to MCE/ HIGH – Figure 6.32 Slow Memory ( ≤= 128 Kbytes) Write Cycle Higher Middle Lower Valid Write Data (Driven by LSI53C895A) Address Address Address MAS1/ (Driven by LSI53C895A) MAS0/ (Driven by LSI53C895A) MCE/...

  • Page 314: Kbytes Rom Read Cycle

    Address out from MOE/, MCE/ HIGH – Data setup to CLK HIGH – Figure 6.33 ≤ 64 Kbytes ROM Read Cycle Valid Higher Lower (Address driven by LSI53C895A; Read Address Address Data Data driven by Memory) MAS1/ (Driven by LSI53C895A)

  • Page 315: Kbyte Rom Write Cycle

    MCE/ LOW to MWE/ LOW – MWE/ HIGH to MCE/ HIGH – Figure 6.34 ≤ 64 Kbyte ROM Write Cycle Higher Lower Valid Write Data (Driven by LSI53C895A) Address Address MAS1/ (Driven by LSI53C895A) MAS0/ (Driven by LSI53C895A) MCE/ (Driven by LSI53C895A)

  • Page 316: Scsi Timing Diagrams

    6.5 SCSI Timing Diagrams Tables 6.40 through 6.50 and Figures 6.35 through 6.39 and describe the LSI53C895A SCSI timing. Table 6.40 Initiator Asynchronous Send Symbol Parameter Unit SACK/ asserted from SREQ/ asserted – SACK/ deasserted from SREQ/ deasserted – Data setup to SACK/ asserted –...

  • Page 317: Initiator Asynchronous Receive

    Table 6.41 Initiator Asynchronous Receive Symbol Parameter Unit SACK/ asserted from SREQ/ asserted – SACK/ deasserted from SREQ/ deasserted – Data setup to SREQ/ asserted – Data hold from SACK/ asserted – Figure 6.36 Initiator Asynchronous Receive SREQ/ n + 1 SACK/ n + 1 SD[15:0]/,...

  • Page 318: Target Asynchronous Send

    Table 6.42 Target Asynchronous Send Symbol Parameter Unit SREQ/ deasserted from SACK/ asserted – SREQ/ asserted from SACK/ deasserted – Data setup to SREQ/ asserted – Data hold from SACK/ asserted – Figure 6.37 Target Asynchronous Send SREQ/ n + 1 SACK/ n + 1 SD[15:0]/,...

  • Page 319: Target Asynchronous Receive

    Table 6.43 Target Asynchronous Receive Symbol Parameter Unit SREQ/ deasserted from SACK/ asserted – SREQ/ asserted from SACK/ deasserted – Data setup to SACK/ asserted – Data hold from SREQ/ deasserted – Figure 6.38 Target Asynchronous Receive SREQ/ n + 1 SACK/ n + 1 SD[15:0]/,...

  • Page 320: Scsi-1 Transfers (Differential 4.17 Mbytes)

    Table 6.45 SCSI-1 Transfers (Differential 4.17 Mbytes) Symbol Parameter Unit Send SREQ/ or SACK/ assertion pulse width – Send SREQ/ or SACK/ deassertion pulse width – Receive SREQ/ or SACK/ assertion pulse width – Receive SREQ/ or SACK/deassertion pulse width –...

  • Page 321: Scsi-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) Or 20.0 Mbytes (16-Bit Transfers) 50 Mhz Clock

    Table 6.47 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes 1, 2 (16-Bit Transfers) 50 MHz Clock Symbol Parameter Unit Send SREQ/ or SACK/ assertion pulse width – Send SREQ/ or SACK/ deassertion pulse width – Receive SREQ/ or SACK/ assertion pulse width –...

  • Page 322: Bit Transfers) Or 40.0 Mbytes (16-Bit Transfers) 80 Mhz Clock

    Table 6.49 Ultra SCSI High Voltage Differential Transfers 20.0 Mbytes (8-Bit Transfers) 1, 2 or 40.0 Mbytes (16-Bit Transfers) 80 MHz Clock Symbol Parameter Unit Send SREQ/ or SACK/ assertion pulse width – Send SREQ/ or SACK/ deassertion pulse width –...

  • Page 323: Initiator And Target Synchronous Transfer

    Table 6.50 Ultra2 SCSI Transfers 40.0 Mbytes (8-Bit Transfers) or 80.0 Mbytes 1, 2 (16-Bit Transfers) Quadrupled 40 MHz Clock Symbol Parameter Unit Send SREQ/ or SACK/ assertion pulse width – Send SREQ/ or SACK/ deassertion pulse width – Receive SREQ/ or SACK/ assertion pulse width –...

  • Page 324: Package Diagrams

    6.6 Package Diagrams This section provides pinout information for both chips. Figure 6.40 pinout information for the LSI53C895A 272-pin BGA and Figure 6.41 pinout information for the LSI53C895A 208-pin PQFP. Table 6.51 provides the 272 BGA pin list by location and Table 6.52...

  • Page 325: Lsi53C895A 272-Pin Bga Top View

    Figure 6.40 LSI53C895A 272-Pin BGA Top View VDD_ SD2+ SD3+ SD4+ SD5- SD6- SD7- RBIAS BIAS SATN+ SBSY+ SACK+ SRST+ SMSG+ SSEL+ SSEL- SD1+ SD1- SD2- SD3- SD4- SD5+ SD6+ SD7+ SDP0- SATN- SBSY- SACK- SRST- SMSG- SREQ2+ SREQ2- SD0-...

  • Page 326: Bga Pin List By Location

    Table 6.51 272 BGA Pin List by Location Signal Signal Signal Signal Signal VDDA IDSEL SCD − DIFFSENS VSSCORE AD21 SD2+ MAD7 AD18 SD3+ SREQ+ SD12+ MAD6 FRAME/ SIO − SD12 − SD4+ VDDCORE SD0+ VDDCORE PERR/ SD5 − SACK2 − AD15 SD6 −...

  • Page 327: Bga Pin List Alphabetically

    Table 6.52 BGA Pin List Alphabetically Signal Signal Signal Pin Signal Signal MAC/ No Connect SD1+ SD2 − TESTOUT No Connect MAD0 No Connect SD2+ SD3 − MAD1 No Connect MAD2 No Connect SD3+ SD4 − MAD3 No Connect MAD4 No Connect SD4+ SD5 −...

  • Page 328: Lsi53C895A 208-Pin Plastic Quad Flat Pack

    Figure 6.41 LSI53C895A 208-Pin Plastic Quad Flat Pack ALT_IRQ/ VDDPCI AD26 AD25 AD24 VSSSCSI C_BE3/ SD1+ VSSPCI SD1− IDSEL SD2+ AD23 SD2− AD22 SD3+ AD21 SD3− VDDPCI VDDSCSI AD20 SD4+ AD19 SD4− SD5+ AD18 AD17 SD5− VSSPCI VSSSCSI AD16 SD6+ C_BE2/ SD6−...

  • Page 329: Signal Names Vs. Pin Number: 208-Pin Plastic Quad Flat Pack

    Table 6.53 Signal Names vs. Pin Number: 208-Pin Plastic Quad Flat Pack Signal Signal Signal Signal Signal SD9 − GPIO0_ No Connect 155 VDDIO FETCH/ No Connect 156 SD9+ VDDIO SD10 − GPIO1_ No Connect 157 VDDIO MASTER/ No Connect 158 SD10+ VDDPCI SD11 −...
  • Page 330 This page intentionally left blank. 6-70 Electrical Specifications...

  • Page 331: Lsi53C895A Vs. Lsi53C895 Pin/Ball Differences

    6.6.1 LSI53C895A vs. LSI53C895 Pin/Ball Differences The LSI53C895A can be used as a drop-in replacement for the LSI53C895. The LSI53C895A is packaged in a 208 PQFP and alternatively a 272 BGA. Note: The BGA package for the LSI53C895 is a 292 BGA with the only difference being the center grid is 6 x 6 balls vs.

  • Page 332: Lsi53C895A Vs. Lsi53C895 Pin/Ball Differences

    Table 6.54 indicates the differences between the LSI53C895A and the LSI53C895 signal names and locations. Table 6.54 LSI53C895A vs. LSI53C895 Pin/Ball Differences Pin/Ball 208 PQFP 272 BGA Name Type Pin # Ball # Description ALT_IRQ/ Previously NC. Alternate Interrupt Request, when...
  • Page 333 The LSI53C895A is little endian only. LSI Logic component dimensions conform to a current revision of the JEDEC Publication 95 standard package outline, using ANSI 14.5Y “Dimensioning and Tolerancing” interpretations. As JEDEC drawings are balloted and updated, changes may have occurred.

  • Page 334: Lsi53C895A 208 Pqfp Mechanical Drawing (Sheet 1 Of 2)

    Figure 6.42 is the mechanical drawing for the 208 PQFP and Figure 6.43 is the mechanical drawing for the 272 PBGA for the LSI53C895A. Figure 6.42 LSI53C895A 208 PQFP Mechanical Drawing (Sheet 1 of 2) Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code P9.
  • Page 335 Figure 6.42 208-Pin PQFP (P9) Mechanical Drawing (Sheet 2 of 2) Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code P9. Package Diagrams...

  • Page 336: Lsi53C895A 272 Pbga Mechanical Drawing

    Figure 6.43 LSI53C895A 272 PBGA Mechanical Drawing Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code IG. 6-76...

  • Page 337: Appendix A Register Summary

    Read Only Expansion ROM Base Address 0x30–0x33 Read/Write 4-12 Header Type 0x0E Read Only Interrupt Line 0x3C Read/Write 4-13 Interrupt Pin 0x3D Read Only 4-14 Latency Timer 0x0D Read/Write Max_Lat 0x3F Read Only 4-15 LSI53C895A PCI to Ultra2 SCSI Controller...

  • Page 338: A.2 Lsi53C895A Scsi Register Map

    Table A.1 LSI53C895A PCI Register Map (Cont.) Register Name Address Read/Write Page Min_Gnt 0x3E Read Only 4-14 Next Item Pointer 0x41 Read Only 4-15 Power Management Capabilities (PMC) 0x42–0x43 Read Only 4-16 Power Management Control/Status (PMCSR) 0x44–0x45 Read/Write 4-17 Reserved 0x28–0x2B...
  • Page 339 Table A.2 LSI53C895A SCSI Register Map (Cont.) Register Name Address Read/Write Page Chip Test Two (CTEST2) 0x1A Read Only (bit 3 4-55 write) Chip Test Zero (CTEST0) 0x18 Read/Write 4-54 Cumulative SCSI Byte Count (CSBC) 0xDC–0xDF Read/Write 4-112 Data Structure Address (DSA) 0x10–0x13...
  • Page 340 Table A.2 LSI53C895A SCSI Register Map (Cont.) Register Name Address Read/Write Page Mailbox One (MBOX1) 0x17 Read/Write 4-53 Mailbox Zero (MBOX0) 0x16 Read/Write 4-53 Memory Access Control (MACNTL) 0x46 Read/Write 4-83 Memory Move Read Selector (MMRS) 0xA0–0xA3 Read/Write 4-103 Memory Move Write Selector (MMWS) 0xA4–0xA7...
  • Page 341 Table A.2 LSI53C895A SCSI Register Map (Cont.) Register Name Address Read/Write Page SCSI Control Two (SCNTL2) 0x02 Read/Write 4-27 SCSI Control Zero (SCNTL0) 0x00 Read/Write 4-21 SCSI Destination ID (SDID) 0x06 Read/Write 4-36 SCSI First Byte Received (SFBR) 0x08 Read/Write...
  • Page 342 Table A.2 LSI53C895A SCSI Register Map (Cont.) Register Name Address Read/Write Page SCSI Timer Zero (STIME0) 0x48 Read/Write 4-85 SCSI Transfer (SXFER) 0x05 Read/Write 4-32 SCSI Wide Residue (SWIDE) 0x45 Read/Write 4-82 Static Block Move Selector (SBMS) 0xB0–0xB3 Read/Write 4-106 Temporary (TEMP) 0x1C–0x1F...

  • Page 343: Appendix B External Memory Interface Diagram Examples

    MAD[7:0] A[7:0] A[13:8] MAD0 4.7 K 27C128 LSI53C895A HCT374 MAS0/ HCT374 MAS1/ Note: MAD[3:1] pulled LOW internally. MAD bus sense logic enabled for 16 Kbyte of slow memory (200 ns devices @ 33 MHz). LSI53C895A PCI to Ultra2 SCSI Controller...

  • Page 344: Kbyte Interface With 150 Ns Memory

    A[7:0] 27C512-15/ A[15:8] 28F512-15/ MAD2 4.7 K Socket LSI53C895A HCT374 MAS0/ HCT374 MAS1/ Note: MAD 3, 1, 0 pulled LOW internally. MAD bus sense logic enabled for 64 Kbyte of fast memory (150 ns devices @ 33 MHz). External Memory Interface Diagram Examples...

  • Page 345: Kbytes, 256 Kbytes, 512 Kbytes, Or 1 Mbyte

    A[7:0] 27C020-15/ A[15:8] 28F020-15/ MAD3 4.7 K Socket A[19:16] LSI53C895A HCT374 MAS0/ HCT374 MAS1/ MAD[3:0] HCT377 Note: MAD[2:0] pulled LOW internally. MAD bus sense logic enabled for 128, 256, 512 Kbytes, or 1 Mbyte of fast memory (150 ns devices @ 33 MHz). The HCT374s may be replaced with HCT377s.

  • Page 346: Kbyte Interface With 150 Ns Memory

    D[7:0] MAD[7:0] A[7:0] MAD3 4.7 K A[15:8] MAD1 4.7 K MAD3 4.7 K LSI53C895A HCT374 MAS0/ HCT374 MAS1/ MAD[2:0] MCE/ HCT377 HCT139 Note: MAD2 pulled LOW internally. MAD bus sense logic enabled for 512 Kbytes of slow memory (150 ns devices, additional time required for HCT139 @ 33 MHz).
  • Page 347 (EBM) (COM) 4-73 (EIS) (CON) 4-25, 4-50 (EMS) (CP) 4-13 (EN64DBMV) 4-101 (CSBC) 4-112 (EN64TIBMV) 4-101 (CSF) 4-95 (ENC) 4-31, 4-36 (CTEST0) 4-54 (ENID) 4-39 (CTEST1) 4-54 (ENNDJ) 4-99 (CTEST2) 4-55 (ENPMJ) 4-98 LSI53C895A PCI to Ultra2 SCSI Controller IX-1...
  • Page 348 (EPC) 4-23 (MG) 4-14 (EPER) (ML) 4-15 (ERBA) 4-12 (MMRS) 4-104 (ERL) 4-69 (MMWS) 4-105 (ERMP) 4-69 (MO[4:0]) 4-34 (ESA) 4-111 (MPEE) 4-60 (EWS) 4-30 (MSG) 4-38, 4-40, 4-46 (EXC) 4-24 (NC) (EXT) 4-92 (NIP) 4-15 (FBL3) 4-60 (OLF) 4-43 (FE) 4-84 (OLF1)
  • Page 349 (SDU) 4-27 (UDC) 4-75, 4-79 (SE) (USE) 4-29 (SEL) 4-38, 4-40, 4-75, 4-78 4-57 (SEL[3:0]) 4-86 (VAL) 4-39 (SEM) 4-50 (VER[2:0]) 4-16 (SFBR) 4-37 (VID) (SFS) 4-105 (VUE0) 4-28 (SGE) 4-75, 4-78 (VUE1) 4-28 (SI) 4-52 (WATN) 4-23 (SID) 4-11 (WIE) (SIDA) 4-18...
  • Page 350 address incrementor (ADCK) 4-62 byte counter (BBCK) 4-62 conversion factor (CCF[2:0]) 4-30 base address register quadrupler 2-22 one (BAR1) 2-3, CLSE 2-6, two (BAR2) 4-10 2-45 zero - I/O (BAR0) compare bidirectional data 5-31 signals phase 5-31 BIOS configuration bits used for parity control and generation 2-27 read command block move...
  • Page 351 disable (Cont.) (ENID) 4-39 halt on parity error or ATN (target only) (DHP) 4-24 SCSI destination ID 5-20 internal load and store (DILS) 4-99 entry storage address (ESA) 4-111 single initiator response (DSI) 4-94 error reporting signals disconnect 2-19 even parity 2-26 disconnect instruction 5-14...
  • Page 352 (LOA) 4-44 read/write instruction 5-22 low voltage differential. See LVDlink 2-34 transfer control instruction 5-26 LSI53C700 compatibility (COM) 4-73 instructions LSI53C895A block move new features interface control signals internal driver SCSI signals SCRIPTS receiver SCSI signals 2-20 SCSI internal RAM...
  • Page 353 MAC/_TESTOUT 3-14 new capabilities (NC) new features in the LSI53C895A 2-56 Next_Item_Ptr (NIP) 4-15 bus programming 3-19 no connections 3-18 pins 2-56 no download mode 2-58 MAD[0] 3-20 no flush 5-33 MAD[3:1] 3-20 store instruction only 5-36 MAD[4] 3-19 not supported 4-9,...
  • Page 354 power (Cont.) SACs 2-21 state D0 2-61 SATN/ status (ATN) 4-40 state D1 2-61 SATNM+- 3-13 state D2 2-62 SBSY/ status (BSY) 4-40 state D3 2-62 SC_D+- 3-13 power state (PWS[1:0]) 4-17 SC_D/ status (C_D) 4-40 prefetch SCLK 3-11 enable (PFEN) 4-72 (SCLK) 4-90...
  • Page 355 SCSI (Cont.) with SATN/ on a start sequence (WATN) 4-23 interrupt status zero (SIST0) 4-77 selected (SEL) 4-75, 4-78 interrupts 2-48 selection or reselection time-out (STO) 4-77, 4-80 isolation mode (ISO) 4-90 selection response logic test (SLT) 4-89 longitudinal parity (SLPAR) 4-81 selection time-out (SEL[3:0]) 4-86...
  • Page 356 start (Cont.) SCSI transfer (SST) 4-26 sequence (START) 4-22 Ultra SCSI static block move selector (SBMS) 4-106 clock conversion factor bits 4-31 STEST2 register 2-26 enable (USE) 4-29 STOP command high voltage differential transfers 20.0 mbytes (8-bit stop signal transfers) or 40.0 mbytes (16-bit transfers) 80 MHz clock STOP/ signal 6-62 store...

  • Page 357: Customer Feedback

    Please include your name, phone number, fax number, and company address so that we may contact you directly for clarification or additional information. Thank you for your help in improving the quality of our documents. LSI53C895A PCI to Ultra2 SCSI Controller...
  • Page 358 LSI Logic Corporation Technical Publications M/S E-198 Fax: 408.433.4333 Please tell us how you rate this document: LSI53C895A PCI to Ultra2 SCSI Controller Technical Manual. Place a check mark in the appropriate blank for each category. Excellent Good Average Fair...
  • Page 359 U.S. Distributors by State A. E. Avnet Electronics Colorado Illinois Michigan http://www.hh.avnet.com Denver North/South Brighton B. M. Bell Microproducts, A. E. Tel: 303.790.1662 A. E. Tel: 847.797.7300 I. E. Tel: 810.229.7710 Inc. (for HAB’s) B. M. Tel: 303.846.3065 Tel: 314.291.5350 Detroit http://www.bellmicro.com W.
  • Page 360 U.S. Distributors by State (Continued) New York South Carolina Washington Hauppauge A. E. Tel: 919.872.0712 Kirkland I. E. Tel: 516.761.0960 W. E. Tel: 919.469.1502 I. E. Tel: 425.820.8100 Long Island Maple Valley South Dakota A. E. Tel: 516.434.7400 B. M. Tel: 206.223.0080 A.
  • Page 361 Direct Sales Representatives by State (Components and Boards) E. A. Earle Associates Texas E. L. Electrodyne - UT Austin Group 2000 Tel: 512.794.9006 I. S. Infinity Sales, Inc. Arlington ION Associates, Inc. Tel: 817.695.8000 R. A. Rathsburg Associ- Houston ates, Inc. Tel: 281.376.2000 Synergy Associates, Utah...
  • Page 362 Sales Offices and Design Resource Centers LSI Logic Corporation Fort Collins New Jersey Canada Corporate Headquarters 2001 Danfield Court Red Bank Ontario Fort Collins, CO 80525 1551 McCarthy Blvd 125 Half Mile Road Ottawa Tel: 970.223.5100 Milpitas CA 95035 Suite 200 260 Hearst Way Tel: 408.433.8000...
  • Page 363 Sales Offices and Design Resource Centers (Continued) Korea Seoul LSI Logic Corporation of Korea Ltd 10th Fl., Haesung 1 Bldg. 942, Daechi-dong, Kangnam-ku, Seoul, 135-283 Tel: 82.2.528.3400 Fax: 82.2.528.2250 The Netherlands Eindhoven LSI Logic Europe Ltd World Trade Center Eindhoven Building ‘Rijder’...
  • Page 364 Switzerland Tel: 44.1793.849933 Bangalore, India 560078 Xicheng District ♦ Brugg Fax: 44.1793.859555 Tel: 91.80.664.5530 Beijing 100045, China LSI Logic Sulzer AG Tel: 86.10.6804.2534 to 38 Fax: 91.80.664.9748 Mattenstrasse 6a Fax: 86.10.6804.2521 ♦ CH 2555 Brugg Sales Offices with Israel Tel: 41.32.3743232...

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