Address And Data Signals - LSI LSI53C896 Technical Manual

3.2.2 Address and Data Signals

Table 3.3 Address and Data Signals
Name Bump
AD[63:0] Y5, AB5, AC5, AA6,
Y6, AB6, AC6, AA7,
AB7, AC7, AA8, Y8,
AB8, AC8, AA9, Y9,
AB9, AC9, AA10,
Y11, AB10, AC10,
AA11, AC11, AB11,
AC12, AA12, AB12,
AB13, AC13, AA13,
AC14, H1, J3, J4,
J2, J1, K3, L4, K2,
L1, L2, M1, M3, M2,
N2, N1, N3, T4, T3,
U1-U3, V1, V2, V4,
W1, W2, W4, W3,
Y1, Y2, AA1, Y3.
C_BE[7:0]/ AA4, AC3, AB4,
AC4, K1, P1, T2, V3.
PAR T1
3-6
Table 3.3 describes the signals for the Address and Data Signals group.
Type
T/S
T/S
T/S
Signal Descriptions
Strength Description
16 mA Physical Dword Address and Data are
PCI multiplexed on the same PCI pins. A bus
transaction consists of an address phase
followed by one or more data phases.
During the first clock of a transaction,
AD[63:0] contain a 64-bit physical byte
address. If the command is a DAC,
implying a 64-bit address, AD[31:0] will
contain the upper 32 bits of the address
during the second clock of the
transaction. During subsequent clocks,
AD[63:0] contain data. PCI supports both
read and write bursts. AD[7:0] define the
least significant byte, and AD[63:56]
define the most significant byte.
16 mA Bus Command and Byte Enables are
*
PCI multiplexed on the same PCI pins.
During the address phase of a
transaction, C_BE[3:0]/ define the bus
command. If the transaction is a DAC,
C_BE[3:0]/ contain the DAC command
and C_BE[7:4]/ define the bus command.
C_BE[3:0]/ define the bus command
during the second clock of the
transaction. During the data phase,
C_BE[7:0]/ are used as byte enables.
The byte enables determine which byte
lanes carry meaningful data. C_BE[0]/
applies to byte 0, and C_BE[7]/ to byte 7.
16 mA Parity is the even parity bit that protects
PCI the AD[31:0] and C_BE[3:0]/ lines.
During the address phase, both the
address and command bits are covered.
During data phase, both data and byte
enables are covered.